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Conexant Proprietary Information Dissemination or use of this information is not permitted without the written permission of Conexant Systems, Inc.
Doc. No. 1213, Rev. 1 January 20, 1999
RH56D-PCI Modem Designer's Guide
Information provided by Conexant Systems, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. K56flex is a trademark of Conexant Systems, Inc. and Lucent Technologies. Conexant and "What's Next in Communications Technologies" are trademarks of Conexant Systems, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective owners.
(c)1999, Conexant Systems, Inc. Printed in U.S.A. All Rights Reserved
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RH56D-PCI Modem Designer's Guide
Table of Contents
1. INTRODUCTION................................................................................................................................................. 1-1 1.1 1.2 1.3 SUMMARY ............................................................................................................................................... 1-1 FEATURES .............................................................................................................................................. 1-3 TECHNICAL OVERVIEW......................................................................................................................... 1-6 1.3.1 General Description ................................................................................................................... 1-6 1.3.2 Host Modem Software................................................................................................................ 1-6 1.3.3 Operating Modes........................................................................................................................ 1-6 Data/Fax Modes................................................................................................................ 1-6 Synchronous Access Mode (SAM) - Video Conferencing................................................. 1-6 Voice/TAM Mode............................................................................................................... 1-7 Speakerphone Mode (SP Model)...................................................................................... 1-7 1.3.4 Hardware Interfaces................................................................................................................... 1-7 PCI Bus Host Interface...................................................................................................... 1-7 Serial EEPROM Interface ................................................................................................. 1-8 Audio Interface .................................................................................................................. 1-8 Telephone Line/Telephone/Audio Interface ...................................................................... 1-8
2.
TECHNICAL SPECIFICATIONS ........................................................................................................................ 2-1 2.1 ESTABLISHING DATA MODEM CONNECTIONS................................................................................... 2-1 Dialing ............................................................................................................................... 2-1 Modem Handshaking Protocol .......................................................................................... 2-1 Call Progress Tone Detection ........................................................................................... 2-1 Answer Tone Detection..................................................................................................... 2-1 Ring Detection................................................................................................................... 2-1 Billing Protection ............................................................................................................... 2-1 Connection Speeds........................................................................................................... 2-1 Automode.......................................................................................................................... 2-1 DATA MODE ............................................................................................................................................ 2-1 Speed Buffering (Normal Mode) ....................................................................................... 2-1 DTE-to-Modem Flow Control............................................................................................. 2-1 Escape Sequence Detection............................................................................................. 2-1 GSTN Cleardown (V.90/K56flex, V.34, V.32 bis, V.32)..................................................... 2-2 Fall Forward/Fallback (V.90/K56flex, V.34/V.32 bis/V.32) ................................................ 2-2 Retrain............................................................................................................................... 2-2 ERROR CORRECTION AND DATA COMPRESSION............................................................................. 2-2 V.42 Error Correction ........................................................................................................ 2-2 MNP 2-4 Error Correction ................................................................................................. 2-2 V.42 bis Data Compression .............................................................................................. 2-2 MNP 5 Data Compression ................................................................................................ 2-2 FAX CLASS 1 OPERATION..................................................................................................................... 2-2 VOICE/TAM MODE .................................................................................................................................. 2-2 2.5.1 Online Voice Command Mode ................................................................................................... 2-2 2.5.2 Voice Receive Mode .................................................................................................................. 2-3 2.5.3 Voice Transmit Mode ................................................................................................................. 2-3 2.5.4 Speakerphone Modes ................................................................................................................ 2-3 FULL-DUPLEX SPEAKERPHONE (FDSP) MODE .................................................................................. 2-3 CALLER ID............................................................................................................................................... 2-3 MULTIPLE COUNTRY SUPPORT ........................................................................................................... 2-3 2.8.1 OEM Programmable Parameters ............................................................................................... 2-3 2.8.2 Blacklist Parameters .................................................................................................................. 2-3 DIAGNOSTICS......................................................................................................................................... 2-4 2.9.1 Commanded Tests..................................................................................................................... 2-4 LOW POWER SLEEP MODE................................................................................................................... 2-4
2.2
2.3
2.4 2.5
2.6 2.7 2.8
2.9 2.10
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RH56D-PCI Modem Designer's Guide
3. HARDWARE INTERFACE ................................................................................................................................. 3-1 3.1 3.2 3.3 3.4 4. HARDWARE SIGNAL PINS AND DEFINITIONS ..................................................................................... 3-1 POWER REQUIREMENTS AND MAXIMUM RATINGS......................................................................... 3-13 MDP ELECTRICAL CHARACTERISTICS.............................................................................................. 3-14 PCI BUS ELECTRICAL, SWITCHING, AND TIMING CHARACTERISTICS.......................................... 3-14
DESIGN CONSIDERATIONS ............................................................................................................................. 4-1 4.1 PC BOARD LAYOUT GUIDELINES......................................................................................................... 4-1 4.1.1 General Principles...................................................................................................................... 4-1 4.1.2 Component Placement............................................................................................................... 4-1 4.1.3 Signal Routing............................................................................................................................ 4-2 4.1.4 Power ......................................................................................................................................... 4-3 4.1.5 Ground Planes ........................................................................................................................... 4-4 4.1.6 Crystal Circuit............................................................................................................................. 4-4 4.1.7 VC and VREF Circuit ................................................................................................................. 4-4 4.1.8 Telephone and Local Handset Interface .................................................................................... 4-5 4.1.9 Optional Configurations ............................................................................................................. 4-5 4.1.10 MDP Specific.............................................................................................................................. 4-5 CUSTOM DESIGN GUIDELINES FOR 2-LAYER PCI MODEM BOARD ................................................. 4-5 4.2.1 General Guidelines .................................................................................................................... 4-5 4.2.2 Placement of Modem Devices ................................................................................................... 4-6 4.2.3 Trace Routing and Length on PCI Signals................................................................................. 4-6 4.2.4 Grounding .................................................................................................................................. 4-6 4.2.5 Filtering ...................................................................................................................................... 4-6 4.2.6 Decoupling ................................................................................................................................. 4-7 4.2.7 Crystal Circuit............................................................................................................................. 4-7 4.2.8 Modem Analog Interface ............................................................................................................ 4-8 PCB LAYOUT EXAMPLES....................................................................................................................... 4-9 CRYSTAL/OSCILLATOR SPECIFICATIONS ........................................................................................ 4-11 OTHER CONSIDERATIONS.................................................................................................................. 4-11 PACKAGE DIMENSIONS....................................................................................................................... 4-14
4.2
4.3 4.4 4.5 4.6 5.
SOFTWARE INTERFACE .................................................................................................................................. 5-1 5.1 PCI CONFIGURATION REGISTERS....................................................................................................... 5-1 5.1.1 0x00 - Vendor ID Field ............................................................................................................... 5-1 5.1.2 0x02 - Device ID Field................................................................................................................ 5-1 5.1.3 0x04 - Command Register ......................................................................................................... 5-2 5.1.4 0x06 - Status Register ............................................................................................................... 5-2 5.1.5 0x08 - Revision ID Field............................................................................................................. 5-3 5.1.6 0x09 - Class Code Field............................................................................................................. 5-3 5.1.7 0x0D - Latency Timer Register .................................................................................................. 5-3 5.1.8 0x0E - Header Type Field .......................................................................................................... 5-3 5.1.9 0x28 - CIS Pointer Register ....................................................................................................... 5-3 5.1.10 0x2C - Subsystem Vendor ID Register ...................................................................................... 5-3 5.1.11 0x2E- Subsystem ID Register .................................................................................................... 5-3 5.1.12 0x34 - Cap Ptr ............................................................................................................................ 5-3 5.1.13 0x3C - Interrupt Line Register .................................................................................................... 5-3 5.1.14 0x3D - Interrupt Pin Register...................................................................................................... 5-3 5.1.15 0x3E - Min Grant Register.......................................................................................................... 5-3 5.1.16 0x3F - Max Latency Register ..................................................................................................... 5-3 5.1.17 0x40 - Capability Identifier ......................................................................................................... 5-3 5.1.18 0x41 - Next Item Pointer ............................................................................................................ 5-3 5.1.19 0x42 - PMC - Power Management Capabilities ......................................................................... 5-4 5.1.20 0x44 - PMCSR - Power Management Control/Status Register (Offset = 4)............................... 5-4 5.1.21 0x46 - PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions..................................... 5-4 5.1.22 0x47 - Data ................................................................................................................................ 5-4
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RH56D-PCI Modem Designer's Guide
5.2 5.3 BASE ADDRESS REGISTER .................................................................................................................. 5-5 SERIAL EEPROM INTERFACE ............................................................................................................... 5-6 5.3.1 Supported EEPROM Sizes ........................................................................................................ 5-6 5.3.2 Definitions .................................................................................................................................. 5-7 Device ID Register ............................................................................................................ 5-7 Vendor ID Register............................................................................................................ 5-7 Subsystem Vendor ID and Subsystem Device Register ................................................... 5-7 Min_Gnt Register .............................................................................................................. 5-7 Max_Lat Register .............................................................................................................. 5-7 PMC [8:6], PME DRV Type ............................................................................................... 5-8 CardBus CIS Pointer (CardBus CIS pointer High, CardBus CIS pointer Low).................. 5-8 Data Register (D3, D2, D1, D0 power consumed and D3, D2, D1, D0 power dissipated)......................................................................................................................... 5-8 Load CISRAM Count (CIS _SIZE) .................................................................................... 5-8
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RH56D-PCI Modem Designer's Guide
List of Figures
Figure 1-1. RH56D-PCI System Overview ............................................................................................................................... 1-4 Figure 1-2. RH56D-PCI Hardware Configuration Block Diagram ............................................................................................. 1-5 Figure 1-3. Typical Audio Signal Interface (U.S.) ..................................................................................................................... 1-9 Figure 3-1. RH56D-PCI Major Hardware Interface Signals ...................................................................................................... 3-2 Figure 3-2. R6795 144-Pin TQFP Hardware Interface Signals ................................................................................................ 3-3 Figure 3-3. R6795 144-Pin TQFP Pin Signals.......................................................................................................................... 3-4 Figure 3-4. Schematic - R6795 Interface -Speakerphone Application................................................................................... 3-12 Figure 4-1. PCICLK Guard Band Technique ............................................................................................................................ 4-9 Figure 4-2. Receive Path Guard-Band, Merge between AGND-GND ...................................................................................... 4-9 Figure 4-3. Crystal Solution .................................................................................................................................................... 4-10 Figure 4-4. Power and Ground Distribution ............................................................................................................................ 4-10 Figure 4-5. Package Dimensions - 144-Pin TQFP ................................................................................................................. 4-14
List of Tables
Table 1-1. Modem Models and Functions ................................................................................................................................ 1-2 Table 1-2. Typical Signal Routing - Voice Mode .................................................................................................................... 1-10 Table 3-1. R6795 144-Pin TQFP Pin Signals........................................................................................................................... 3-5 Table 3-2. R6795 Pin Signal Definitions................................................................................................................................... 3-7 Table 3-3. Current and Power Requirements ......................................................................................................................... 3-13 Table 3-4. Absolute Maximum Ratings................................................................................................................................... 3-13 Table 3-5. Analog Electrical Characteristics........................................................................................................................... 3-14 Table 4-1. Crystal Specifications - Surface Mount ................................................................................................................. 4-12 Table 4-2. Crystal Specifications - Through Hole ................................................................................................................... 4-13 Table 5-1. PCI Configuration Registers.................................................................................................................................... 5-1 Table 5-2. Command Register ................................................................................................................................................. 5-2 Table 5-3. Status Register........................................................................................................................................................ 5-2 Table 5-4. Power Management Capabilities (PMC) Register ................................................................................................... 5-4 Table 5-5. Power Management Control/Status Register (PMCSR).......................................................................................... 5-4 Table 5-6. BIF Address Map..................................................................................................................................................... 5-5 Table 5-7. EEPROM Content for 256 Words by 16 Bits per Word ........................................................................................... 5-6 Table 5-8. EEPROM Content for 128 Words by 16 Bits per Word ........................................................................................... 5-6
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RH56D-PCI Modem Designer's Guide 1. INTRODUCTION
1.1 SUMMARY
The Conexant RH56D-PCI V.90/K56flexTM Host Controlled Modem Device Family supports high speed analog data up to 56 kbps, 14.4 kbps fax, voice/TAM, and speakerphone (optional) operation. The modem operates with PSTN telephone lines in the U.S. and world-wide. The modem is available with or without speakerphone support (see Table 1-1). The modem is packaged in a single 144-pin thin quad flat pack (TQFP) that combines PCI Bus Interface (BIF) and Modem Data Pump (MDP) functions. This modem is pin-compatible with the SoftK56-PCI modem, part number R6793 (see SoftK56-PCI data sheet Order No. MD231). Host modem software is also provided. Operating with +3.3V power, this device set supports 32-bit host applications in such designs as embedded motherboards and PCI half cards. Downloadable architecture allows updating of MDP executable code. Figure 1-1 illustrates the general structure of the RH56D-PCI software and the interface to the RH56D-PCI hardware. Figure 1-2 illustrates the major hardware interfaces supported by each model. In ITU-T V.90/K56flex data mode, the modem can receive data at speeds up to 56 kbps from a digitally connected V.90 or K56flex-compatible central site modem. A V.90/K56flex modem takes advantage of the PSTN which is primarily digital except for the client modem to central office local loop and is ideal for applications such as remote access to an Internet Service Provider (ISP), on-line service, or corporate site. In this mode, the modem can transmit data at speeds up to V.34 rates. In V.34 data mode, the modem operates at line speeds up to 33.6 kbps. When applicable, error correction (V.42/MNP 2-4) and data compression (V.42 bis/MNP 5) maximize data transfer integrity and boost average data throughput. Non-errorcorrecting mode is also supported. All models support remote audio recording and remote audio playback over the telephone line interface using A-Law, -Law, or linear coding at 8000 or 7200 Hz sample rate to support applications such as digital telephone answering machine (TAM). The SP model supports position independent, full-duplex speakerphone (FDSP) operation. Fax Group 3 send and receive rates are supported up to 14.4 kbps with T.30 protocol. V.80 synchronous access mode supports host-controlled communication protocols, e. g., H.324 video conferencing. Reference design kits are available to minimize application design time and costs. This designer's guide describes the modem hardware capabilities and identifies the supporting commands. Commands and parameters are defined in the Commands for RH56D/RC56HCF and RH56LD Reference Manual (Order No. 1118).
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RH56D-PCI Modem Designer's Guide
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RH56D-PCI Modem Designer's Guide
1.2 FEATURES
* Data modem - ITU-T V.90, K56flex, V.34 (33.6 kbps), V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21; Bell 212A and 103 - V.42 LAPM and MNP 2-4 error correction - V.42 bis and MNP 5 data compression - V.250 (ex V.25 ter) and V.251 (ex V.25 ter Annex A) commands - Fax modem send and receive rates up to 14.4 kbps ITU-T V.17, V.29, V.27 ter, and V.21 channel 2 - EIA/TIA 578 Class 1 and T.31 Class 1.0 commands * Voice, telephony, TAM - V.253 commands - 8-bit -Law/A-Law coding (G.711) - 8-bit/16-bit linear coding - 8000/7200 Hz sample rate - Music on hold from host or analog hardware input - TAM support with concurrent DTMF detect, ring detect and caller ID * V.80 synchronous access mode supports host-controlled communication protocols - H.324 interface support * V.8/V.8bis and V.251 (ex V.25 ter Annex A) commands * Full-duplex Speakerphone (FDSP) Mode (SP model) - Telephone handset interface - External microphone and speaker interface - Microphone gain and muting - Speaker volume control and muting - Adaptive acoustic, line, and handset echo cancellation - Loop gain control, transmit and receive path AGC * Data/Fax/Voice call discrimination * Multiple country support - Call progress, blacklisting * Single profile stored in host * Modem and audio paths concurrent across PCI Bus * System compatibilities - Windows 95, Windows 95 OSR2, Windows 98, Windows NT 4.0, Windows NT 5.0 operating systems - Microsoft's PC 98 Design Initiative compliant - Unimodem/V compliant - Pentium 133 MHz equivalent or greater - 16 Mbyte RAM or more * 32-bit PCI Local Bus interface - Conforms to the PCI Local Bus Specification, Production Version, Revision 2.1 - PCI Bus Mastering interface to the MDP - 33 MHz PCI clock support * Supports PCI Bus Power Management - Conforms to PCI Bus Power Management Specification, Rev. 1.1 - ACPI Power Management Registers - APM support - PME# support * Device package - R6795 Modem: 144-pin TQFP (1.6 mm max. height) * +3.3V operation with +5V tolerant digital inputs * +5V or +3.3V analog operation
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RH56D-PCI Modem Designer's Guide
PC Software
Win32-based communications application
Win16-based communications application
MS-DOS application (MS-DOS Box)
Win95 Communications Stack
RH56D-PCI Serial Port Driver*
Modem Hardware on Motherboard or Plug-in Module
RH56D-PCI Modem Device Hardware*
Bus Interface (BIF) and Modem Data Pump (MDP) Functions
*CONEXANT supplied
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RH56D-PCI Modem Designer's Guide
RH56D-PCI MODEM DEVICE
PCI BUS
COMBINED PCI BUS INTERFACE AND MODEM DATA PUMP [R6795-12: 144-PIN TQFP]
TELEPHONE LINE/ TELEPHONE HANDSET/ MIC AND SPEAKER INTERFACE CIRCUIT
PSTN TELEPHONE LINE
DIGITAL SPEAKER (CALL PROGRESS)
a. Typical Interface for Data/Fax/Remote TAM
PSTN TELEPHONE LINE
RH56D/SP-PCI MODEM DEVICE
PCI BUS
COMBINED PCI BUS INTERFACE AND MODEM DATA PUMP [R6795-11: 144-PIN TQFP]
TELEPHONE LINE/ TELEPHONE HANDSET/ MIC AND SPEAKER INTERFACE CIRCUIT
HANDSET (OPTIONAL) [SP MODEL] MIC (OPTIONAL) [SP MODEL] SPEAKER (OPTIONAL) [SP MODEL]
DIGITAL SPEAKER (CALL PROGRESS)
b. Typical Interface for Data/Fax/Voice/Speakerphone
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RH56D-PCI Modem Designer's Guide
1.3 TECHNICAL OVERVIEW
1.3.1 General Description The RH56D-PCI modem provides the processing core for a complete system design featuring data/fax modem, voice/TAM, and speakerphone support, depending on specific model (Table 1-1). Note: The term, "RH56D-PCI Device Set", refers to the family of modem models listed in Table 1-1. Modem operation, including dialing, call progress, telephone line interface, telephone handset interface, audio interface, and host interface functions are supported and controlled through the command set. The modem hardware connects to the host processor via a PCI Bus interface. The OEM adds a crystal circuit, EEPROM, telephone line interface, telephone handset interface (optional), and audio interface (optional) to complete the system. 1.3.2 Host Modem Software The host modem software performs two distinct tasks: 1. 2. General modem control which includes command sets, fax Class 1, voice/TAM, speakerphone, error correction, data compression, and operating system interface functions. Modem data pump control. Binary executable code controlling MDP operation is downloaded as required during operation.
Configurations of the modem software are provided to support modem models listed in Table 1-1. Binary executable modem software is provided for the OEM. 1.3.3 Operating Modes Data/Fax Modes As a V.90/K56flex data modem, the modem can receive data from a digital source using a V.90- or K56flex-compatible central site modem over the digital telephone network portion of the PSTN at line speeds up to 56 kbps. Asymmetrical data transmission supports sending data up to V.34 rates. This mode can fallback to full-duplex V.34 mode, and to slower rates as dictated by line conditions. As a V.34 data modem, the modem can operate in 2-wire, full-duplex, asynchronous modes at line rates up to 33.6 kbps. Data modem modes perform complete handshake and data rate negotiations. Using V.34 modulation to optimize modem configuration for line conditions, the modem can connect at the highest data rate that the channel can support from 33600 bps down to 2400 bps with automatic fallback. Automode operation in V.34 is provided in accordance with PN3320 and in V.32 bis in accordance with PN2330. All tone and pattern detection functions required by the applicable ITU or Bell standard are supported. In fax modem mode, the modem can operate in 2-wire, half-duplex, synchronous modes and can support Group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800, or 2400 bps. Fax data transmission and reception performed by the modem are controlled and monitored through the fax EIA/IA-578 Class 1 and T.31 Class 1.0 command interface. Full HDLC formatting, zero insertion/deletion, and CRC generation/checking are provided. Both transmit and receive fax data are buffered within the modem. Data transfer to and from the DTE is flow controlled by XON/XOFF and RTS/CTS. Synchronous Access Mode (SAM) - Video Conferencing V.80 synchronous access mode between the modem and the host/DTE is provided for host-controlled communication protocols, e.g., H.324 video conferencing applications. Voice-call-first (VCF) before switching to a videophone call is also supported.
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RH56D-PCI Modem Designer's Guide
Voice/TAM Mode Voice/TAM Mode features include 8-bit -Law, A-Law, and linear coding at 8000 Hz and 7200 Hz sample rates. Tone detection/generation, call discrimination, and concurrent DTMF detection are also supported. ADPCM (4-bit IMA) coding is also supported to meet Microsoft WHQL logo requirements. Voice/TAM Mode is supported by three submodes: 1. 2. 3. Online Voice Command Mode supports connection to the telephone line or, for the SP model, a handset. Voice Receive Mode supports recording voice or audio data input at the RIN pin, typically from the telephone line or, for the SP model, a microphone/handset. Voice Transmit Mode supports playback of voice or audio data to the TXA1/TXA2 output, typically to the telephone line or, for the SP model, a speaker/handset.
Speakerphone Mode (SP Model) The SP model includes additional telephone handset, external microphone, and external speaker interfaces which support voice and full-duplex speakerphone (FDSP) operation. Hands-free full-duplex telephone operation is supported in Speakerphone Mode under host control. Speakerphone Mode features an advanced proprietary speakerphone algorithm which supports full-duplex voice conversation with acoustic, line, and handset echo cancellation. Parameters are constantly adjusted to maintain stability with automatic fallback from fullduplex to pseudo-duplex operation. The speakerphone algorithm allows position independent placement of microphone and speaker. The host can separately control volume, muting, and AGC in microphone and speaker channels. 1.3.4 Hardware Interfaces PCI Bus Host Interface The Bus Interface conforms to the PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995. It is a memory slave (burst transactions) and a bus master for PC host memory accesses (burst transactions). Configuration is by PCI configuration protocol. The following interface signals are supported: * Address and data - 32 bidirectional Address/Data (AD[31-0]; bidirectional - Four Bus Command and Byte Enable (CBE [3:0]), bidirectional - Bidirectional Parity (PAR); bidirectional * Interface control - Cycle Frame (FRAME#); bidirectional - Initiator Ready (IRDY#); bidirectional - Target Ready (TRDY#); bidirectional - Stop (STOP#); bidirectional - Initialization Device Select (IDSEL); input - Device Select (DEVSEL#); bidirectional * Arbitration - Request (REQ#); output - Grant (GRANT#); input * Error reporting - Parity Error (PERR#); bidirectional - System Error ; bidirectional * System - Interrupt A (INTA#); output - Clock (PCICLK); input - Reset (PCIRST#); input * Power Management - Power Management Event (PME#), output - Vaux Detect (VauxDET), input
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RH56D-PCI Modem Designer's Guide
Serial EEPROM Interface A serial EEPROM is required to store the Maximum Latency, Minimum Grant, Device ID, Vendor ID, Subsystem ID, and Subsystem Vendor ID parameters for the PCI Configuration Space Header. The serial EEPROM interface connects to an Microchip 93LC66B (256 x 16), 93LC56B (128 x 16), Atmel AT93C66 (256 x 16), AT93C56 (128 x 16), or equivalent serial EEPROM rated at 1 MHz (SROMCLK is 537.6 kHz). Its size can be reduced from the total of 4096 (256 x 16) bits down to 2048 (128 x 16) bits in non-PC card applications. The interface signals are: a serial data input line from the EEPROM (SROMIN), a serial data output line to the EEPROM (SROMOUT), Clock to the EEPROM (SROMCLK), and chip select to the EEPROM (SROMCS). The EEPROM is programmable by the PC via the R6795 device (see Section 5.3). Audio Interface A digital speaker output (DSPKOUT), or analog speaker output (SPKOUT) available in the SP models, is supported on separate pins, as selected by a bit in the INF file. Both outputs cannot be active at the same time. The digital speaker output (DSPKOUT) provides square wave call progress or carrier signals, which can be optionally connected to a low-cost on-board speaker, e.g., a sounducer, without the use of an external op-amp. This output is used for call progress in Data/Fax mode only where sound quality is not important. The MIC_V and SPKOUT lines, supported in SP model, connect to an external microphone and external speaker to support functions such as speakerphone mode, telephone emulation, microphone voice record, speaker voice playback, and call progress monitor. The SPKOUT output should be used in speakerphone designs where sound quality is important. The analog microphone input (MIC_V) can also accept an external audio signal to support functions such as speakerphone mode, telephone emulation, microphone voice record, and music on hold. Also, for the SP models, a telephone input (TELIN) is supported for optionally connecting the modem to a telephone handset microphone and a telephone output (TELOUT) is supported for optionally connecting the modem to a telephone handset speaker. Telephone Line/Telephone/Audio Interface The Telephone Line/Telephone/Audio Signal Interface can support a 3-relay telephone line interface (Figure 1-3). Signal routing for Voice mode is shown in Table 1-2. The following signals are supported: * A single-ended Receive Analog input (RXA) input and a differential Transmit Analog output (TXA1 and TXA2) output. * An Off-hook (OH#) relay control output for connecting the modem to the telephone line. * A Caller ID (CID) relay control output for optionally connecting the telephone line to the modem for Caller ID data extraction. * A Voice (VOICE#) relay control output for optionally switching the telephone line connection between the modem and the telephone handset. * A Ring Indicate (IRING#) input for sensing a raw incoming ring signal. * A Loop Current Sense (LCS#) input for optionally sensing the local primary telephone off-hook status. * An Extension Off-Hook (EXT_L#) input for optionally sensing local extension telephone off-hook status. * Remote Hang-up (LCS_L#/RH_L#) input for optionally sensing remote telephone off-hook status. * Telephone input (TELIN) for connection to a microphone or telephone handset (SP model). * Telephone output (TELOUT) for connection to a speaker or telephone handset (SP model).
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RH56D-PCI Modem Designer's Guide
IRING# RINGWAKE# CID#
CID RELAY
TXA1/TXA2/RXA
XFRMR
SSI & BRDGE OH RELAY
RING DETECT
TEL LINE
OH# LCS#
CUR SRC HANDSET HOOK STATUS DETECT
MODEM DEVICE SET
TELIN/TELOUT
TEL HANDSET
VOICE RELAY
VOICE#
TELEPHONE LINE/TELEPHONE HANDSET INTERFACE CIRCUIT
MIC_M MIC_V MICROPHONE
BIAS
SPKROUT_M*
AMP/ SOUNDUCER (OPTIONAL) SOUNDUCER (LOW COST OPTIONAL)
HEADPHONE
SPKMD*
AUDIO/HEADPHONE INTERFACE CIRCUIT
* USE ONLY ONE OUTPUT.
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RH56D-PCI Modem Designer's Guide
7DEOH 7\SLFDO 6LJQDO 5RXWLQJ 9RLFH 0RGH
+VLS= Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 129
Description
Input Selected
Output Selected
OH# Output Activated No Yes No Yes No Yes No Yes
VOICE# Output Activated No Yes Yes No No Yes No Yes No Yes Yes No Yes Yes No Yes
CID# Output Activated Yes No Yes No Yes No Yes No Yes No No Yes No No Yes No
Modem on hook; phone connected to Line Modem connected to Line Modem connected to Handset Modem connected to Line and Handset Modem connected to Speaker Modem connected to Line and Speaker Modem connected to Microphone Modem connected to Speaker Modem connected to Line and Speaker Modem connected to Microphone RXA MIC_V TXA1/TXA2, SPKOUT TXA1/TXA2, SPKOUT SPKOUT TXA1/TXA2 Speaker and Mic routed to Line via Modem RXA, MIC_V Speaker and Mic routed to Line via Modem RXA, MIC_V Speaker and Mic routed to Line via Modem RXA, MIC_V Modem connected to Headset Mute Speakerphone Microphone Unmute Speakerphone Microphone Mute Speakerphone Speaker Unmute Speakerphone Speaker Modem off-hook, local phone connected to the line. Typically used for music during handset conversation. MIC_V MIC_V MIC_V MIC_V SPKOUT SPKOUT TXA Speaker and Mic routed to Line via Modem RXA, MIC_V RXA MIC_V SPKOUT TXA1/TXA2, SPKOUT TXA1/TXA2, SPKOUT RXA TELIN RXA TXA1/TXA2 TELOUT TXA SPKOUT TXA1/TXA2, SPKOUT
Speaker and Mic routed to Line via Modem TXA1/TXA2
No Yes Yes No Yes Yes No Yes
Yes
Yes
No
130
Modem off-hook, local phone disconnected MIC_V from the line. Typically used to play greeting from audio codec.
TXA
Yes
Yes
No
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RH56D-PCI Modem Designer's Guide 2. TECHNICAL SPECIFICATIONS
2.1 ESTABLISHING DATA MODEM CONNECTIONS
Dialing DTMF Dialing. DTMF dialing using DTMF tone pairs is supported in accordance with ITU-T Q.23. The transmit tone level complies with Bell Publication 47001. Pulse Dialing. Pulse dialing is supported in accordance with EIA/TIA-496-A. Blind Dialing. The modem can blind dial in the absence of a dial tone if enabled by the X0, X1, or X3 command. Modem Handshaking Protocol If a tone is not detected within the time specified in the S7 register after the last digit is dialed, the modem aborts the call attempt. Call Progress Tone Detection Ringback, equipment busy, and progress tones can be detected in accordance with the applicable standard represented by the country profile currently in affect. Answer Tone Detection Answer tone can be detected over the frequency range of 2100 40 Hz in ITU-T modes and 2225 40 Hz in Bell modes. Ring Detection A ring signal can be detected from a TTL-compatible square wave input (frequency is country-dependent). Billing Protection When the modem goes off-hook to answer an incoming call, both transmission and reception of data are prevented for a period of time determined by country requirement to allow transmission of the billing signal. Connection Speeds Data modem line speed can be selected using the +MS command in accordance with V.25 ter. The +MS command selects modulation, enables/disables automode, and selects transmit and receive minimum and maximum line speeds. Automode Automode detection can be enabled by the +MS command to allow the modem to connect to a remote modem in accordance with V.25 ter.
2.2 DATA MODE
Data mode exists when a telephone line connection has been established between modems and all handshaking has been completed. Speed Buffering (Normal Mode) Speed buffering allows a DTE to send data to, and receive data from, a modem at a speed different than the line speed. The modem supports speed buffering at all line speeds. DTE-to-Modem Flow Control If the modem-to-line speed is less than the DTE-to-modem speed, the modem supports XOFF/XON or RTS/CTS flow control with the DTE to ensure data integrity. Escape Sequence Detection The "+++" escape sequence can be used to return control to the command mode from the data mode. Escape sequence detection is disabled by an S2 Register value greater than 127.
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RH56D-PCI Modem Designer's Guide
GSTN Cleardown (V.90/K56flex, V.34, V.32 bis, V.32) Upon receiving GSTN Cleardown from the remote modem in a non-error correcting mode, the modem cleanly terminates the call. Fall Forward/Fallback (V.90/K56flex, V.34/V.32 bis/V.32) During initial handshake, the modem will fallback to the optimal line connection within K56flex/V.34/V.32 bis/V.32 mode depending upon signal quality if automode is enabled by the +MS command. When connected in V.90/K56flex/V.34/V.32 bis/V.32 mode, the modem will fall forward or fallback to the optimal line speed within the current modulation depending upon signal quality if fall forward/fallback is enabled by the %E1 command. Retrain The modem may lose synchronization with the received line signal under poor line conditions. If this occurs, retraining may be initiated to attempt recovery depending on the type of connection. The modem initiates a retrain if line quality becomes unacceptable if enabled by the %E command. The modem continues to retrain until an acceptable connection is achieved, or until 30 seconds elapse resulting in line disconnect.
2.3 ERROR CORRECTION AND DATA COMPRESSION
V.42 Error Correction V.42 supports two methods of error correction: LAPM and, as a fallback, MNP 4. The modem provides a detection and negotiation technique for determining and establishing the best method of error correction between two modems. MNP 2-4 Error Correction MNP 2-4 is a data link protocol that uses error correction algorithms to ensure data integrity. Supporting stream mode, the modem sends data frames in varying lengths depending on the amount of time between characters coming from the DTE. V.42 bis Data Compression V.42 bis data compression mode operates when a LAPM or MNP connection is established. The V.42 bis data compression employs a "string learning" algorithm in which a string of characters from the DTE is encoded as a fixed length codeword. Two dictionaries, dynamically updated during normal operation, are used to store the strings. MNP 5 Data Compression MNP 5 data compression mode operates during an MNP connection. In MNP 5, the modem increases its throughput by compressing data into tokens before transmitting it to the remote modem, and by decompressing encoded received data before sending it to the DTE.
2.4 FAX CLASS 1 OPERATION
Facsimile functions operate in response to Fax Class 1 commands when +FCLASS=1 or +FCLASS=1.0. In the fax mode, the on-line behavior of the modem is different from the data (non-fax) mode. After dialing, modem operation is controlled by fax commands. Some AT commands are still valid but may operate differently than in data modem mode. Calling tone is generated in accordance with T.30.
2.5 VOICE/TAM MODE
Voice and audio functions are supported by the Voice Mode. Voice Mode includes three submodes: Online Voice Command Mode, Voice Receive Mode, and Voice Transmit Mode. 2.5.1 Online Voice Command Mode This mode results from the connection to the telephone line or a voice/audio I/O device (e.g., microphone or speaker) through the use of the +FCLASS=8 and +VLS commands. After mode entry, AT commands can be entered without aborting the connection.
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RH56D-PCI Modem Designer's Guide
2.5.2 Voice Receive Mode This mode is entered when the +VRX command is active in order to record voice or audio data input, typically from a microphone or the telephone line. Received analog voice samples are converted to digital form and compressed for reading by the host. AT commands control the codec sample rate. Received analog mono audio samples are converted to digital form and formatted into 8-bit -Law, A Law, linear, or 4-bit IMA ADPCM format for reading by the host. AT commands control the bit length and sampling rate. Concurrent DTMF/tone detection is available. 2.5.3 Voice Transmit Mode This mode is entered when the +VTX command is active in order to playback voice or audio data, typically to a speaker or to the telephone line. Concurrent DTMF/tone detection is available. Digitized audio data is converted to analog form. 2.5.4 Speakerphone Modes Speakerphone modes are selected in voice mode with the following commands: Speakerphone ON/OFF (+VSP). This command turns the Speakerphone function ON (+VSP = 1) or OFF (+VSP = 0). Microphone Gain (+VGM=). This command sets the microphone gain of the Speakerphone function. Speaker Gain (+VGS=). This command sets the speaker gain of the Speakerphone function.
2.6 FULL-DUPLEX SPEAKERPHONE (FDSP) MODE
The modem operates in FDSP mode when +FCLASS=8 and +VSP=1 (see 2.5.4). In FDSP Mode, speech from a microphone or handset is converted to digital form, shaped, and output to the telephone line through the line interface circuit. Speech received from the telephone line is shaped, converted to analog form, and output to the speaker or handset. Shaping includes both acoustic and line echo cancellation.
2.7 CALLER ID
Caller ID can be enabled/disabled using the +VCID command. When enabled, caller ID information (date, time, caller code, and name) can be passed to the DTE in formatted or unformatted form. Inquiry support allows the current caller ID mode and mode capabilities of the modem to be retrieved from the modem. The retrieval of the Caller ID via an explicit AT query at a later time is essential for implementing a compliant "Instantly available PC" concept.
2.8 MULTIPLE COUNTRY SUPPORT
All models support modem operation in various countries. The country choice is made via the AT+GCI command or country select applet from within those installed in Windows registry. The following capabilities are provided in addition to the data modem functions previously described. Country dependent parameters are included in the .INF file for customization by the OEM Programmable Parameters 2.8.1 OEM Programmable Parameters The following parameters are programmable: * Dial tone detection levels and frequency ranges. * DTMF dialing transmit output level, DTMF signal duration, and DTMF interdigit interval parameters. * Pulse dialing parameters such as make/break times, set/clear times, and dial codes. * Ring detection frequency range. * Blind dialing disable/enable. * The maximum, minimum, and default carrier transmit level values. * Calling tone, generated in accordance with V.25, may also be disabled. * Call progress frequency and tone cadence for busy, ringback, congested, dial tone 1, and dial tone 2. * Answer tone detection period. * On-hook/off-hook, make/break, and set/clear relay control parameters. 2.8.2 Blacklist Parameters The modem can operate in accordance with requirements of individual countries to prevent misuse of the network by limiting repeated calls to the same number when previous call attempts have failed. Call failure can be detected for reasons such as no dial tone, number busy, no answer, no ringback detected, voice (rather than modem) detected, and key abort (dial attempt aborted by user). Actions resulting from such failures can include specification of minimum inter-call delay, extended delay
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RH56D-PCI Modem Designer's Guide
between calls, and maximum numbers of retries before the number is permanently forbidden ("blacklisted"). Up to 20 such numbers may be tabulated. The blacklist parameters are programmable. The current blacklisted and delayed numbers can be queried via AT*B and AT*D commands, respectively.
2.9 DIAGNOSTICS
2.9.1 Commanded Tests Diagnostics are performed in response to the &T1 command per V.54. Analog Loopback (&T1 Command). Data from the local DTE is sent to the modem, which loops the data back to the local DTE. Last Call Status Report (#UD). This command reports the status of the last call.
2.10 LOW POWER SLEEP MODE
When not connected in data, fax, or speakerphone mode, the MDP is placed in a low power state.
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RH56D-PCI Modem Designer's Guide 3. HARDWARE INTERFACE
3.1 HARDWARE SIGNAL PINS AND DEFINITIONS
The RH56D-PCI major functional interface signals are shown in Figure 3-1. The R6795 144-pin TQFP hardware interface signals are shown in Figure 3-2. The R6795 144-pin TQFP pin signals are shown in Figure 3-3 and are listed in Table 3-1. The R6795 144-pin TQFP pin signals are defined in Table 3-2. A schematic showing the R6795 interface for a typical application (data/fax/speakerphone) is shown in Figure 3-4.
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RH56D-PCI Modem Designer's Guide
28.224 MHZ CRYSTAL CIRCUIT
XIN XOUT
PCI BUS
VIO PCICLK PCIRESET# FRAME# IDSEL DEVSEL# IRDY# TRDY# PAR REQ# GNT# INTA# STOP# PERR# SERR# CBE0# CBE1# CBE2# CBE3# AD[31:0] PME# VauxDET
RH56D-PCI SINGLE DEVICE MODEM [R6795: 144-PIN TQFP]
OH# (GPIO0) CID# (GPIO1) VOICE# (GPIO2) LCS# (INPUT2) IRING# (INPUT3) EXT_L# (INPUT4) LCS_L#/RH_L# (INPUT5) RXA TXA1 TXA2 TELIN* TELOUT*
DAA AND TELEPHONE INTERFACE
DSPKOUT SPKOUT* MIC_V* SPKMUTE (GPIO8)
AUDIO INTERFACE
POWER DETECTION AND SWITCHING CIRCUIT +3.3V (VDD) +3.3VA OR +5VA GND AGND
VpciEN# VauxEN# VpciDET
SROMCLK SROMCS SROMOUT SROMIN
VDD AVDD GND AGND * SP MODEL ONLY.
256 x 16 OR 128 X 16 SERIAL EEPROM
MD239F2 R6795 SI
)LJXUH 5+'3&, 0DMRU +DUGZDUH ,QWHUIDFH 6LJQDOV
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RH56D-PCI Modem Designer's Guide
27pF 5% 83 28.224 MHz 1M 82 27pF 5% 44 43 42 41 39 38 37 36 32 31 29 28 27 26 24 23 11 10 9 8 6 5 4 3 138 137 136 134 133 132 131 130 33 22 12 139 126 13 144 16 14 15 21 128 127 123 17 18 19 85 124 1 140 114 116 117 125 2 7 20 25 30 34 40 71 79 81 97 105 115 135 59 54 55 70 78 67 57 35 84 98 113 141 142 143 XOUT AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# PCICLK FRAME# IDSEL DEVSEL# IRDY# TRDY# PAR REQ# GNT# INTA# STOP# PERR# SERR# PME# PCIRST# VIO VIO VauxDET VauxEN# VpciEN# VpciDET VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD AVDD AGND AGND AGND AGND AGNDM AGNDV/NC* GND GND GND GND GND GND GND
MD239F3 HIS R6795
XIN
SROMCS SROMCLK SROMIN SROMOUT RINGWAKE# (INPUT0) OH# (GPIO0) CID# (GPIO1) VOICE# (GPIO2) LCS# (INPUT2) IRING# (INPUT3) EXT_L# (INPUT4) LCS_L#/RH_L# (INPUT 5) RXA TXA1 TXA2
119 122 121 120 106 104 103 102 108 110 111 112 66 61 62
+3.3V EEPROM
10K
DAA
VREF
63 10 0.1 CER
VC SPKMUTE (GPIO8) DSPKOUT SPKOUT* MIC_V/NC* TELIN/NC* TELOUT/NC*
64 100 69 60 65 56 58 10 0.1 CER
AUDIO CIRCUIT FB
SLEEPO (GPIO15) IASLEEP M_CLK V_SCLK M_SCLK V_STROBE M_STROBE V_TXSIN M_TXSIN V_RXOUT M_RXOUT V_CTRL M_CTRL MCTRLSIN VCTRLSIN/NC* MRXOUT VRXOUT/NC* MTXSIN VTXSIN/NC* MSTROBE VSTROBE/NC* MSCLK VSCLK/NC* MCLKIN VCLKIN/NC* GPOL1 GPIO3 GPIO14 INPUT1 NC
46 53 95 88 93 90 91 87 94 89 92 86 96 72 52 76 48 74 50 77 47 75 49 73 51 118 101 99 107 109
PCI BUS
RH56D-PCI R6795 144-PIN TQFP
NC
POWER DETECTION AND SWITCHING CIRCUIT
SET3V# CLKRUN#
80 129
NC (AVDD = +5V) or GND (AVDD = +3.3V)
+3.3V
DRESET# (GPOL0) RESET#
45 68
+3.3VA or +5VA
AGND
GND
)LJXUH 5 3LQ 74)3 +DUGZDUH ,QWHUIDFH 6LJQDOV
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RH56D-PCI Modem Designer's Guide
LCS_L#/RH_L# (INPUT5) EXT_L# (INPUT4) 112 111
IRING# (INPUT3) 110
SROMOUT
SROMCLK
CLKRUN#
SROMCS
VauxDET
VauxEN# VDD
VpciDET PCIRST#
SROMIN
VpciEN#
PCICLK
GPOL1
CBE3#
IDSEL
INTA#
REQ#
GNT#
AD24
AD25
AD26
VDD AD27
AD28
AD29
AD30
AD31
GND
GND
GND
GND
VIO
144
143
142
141
140
139
138
137 136
135
134
133
132
131
130
129
128 127
126
125
124
123
122
121
120
119
118 117
116
115
114
113
109
NC
VIO VDD AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# VDD PAR CBE1# AD15 AD14 VDD AD13 AD12 AD11 AD10 VDD AD9 AD8 CBE0# VDD GND AD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
LCS# (INPUT2) INPUT1 RINGWAKE# (INPUT0) VDD OH# (GPIO0) CID# (GPIO1) VOICE# (GPIO2) GPIO3 SPKMUTE (GPIO8) GPIO14 GND VDD M_CTRL M_CLK M_TXSIN M_SCLK M_RXOUT M_STROBE V_STROBE V_RXOUT V_SCLK V_TXSIN V_CTRL PME# GND XIN XOUT VDD SET3V# VDD AGND MSTROBE MRXOUT MSCLK MTXSIN MCLKIN
SLEEPO (GPIO15)
VSTROBE/NC*
VSCLK/NC* VTXSIN/NC*
VRXOUT/NC*
DRESET# (GPOL0)
VCLKIN/NC* VCTRLSIN/NC*
IASLEEP
VDD AD3
AD6
AD5
AD4
AD2
AD1 AD0
AGND TELIN/NC* AGNDV/NC* TELOUT/NC*
AVDD SPKOUT/NC*
AGND
RESET# DSPKOUT
RXA AGNDM
TXA1
TXA2 VREF
VC MIC_V/NC*
VDD MCTRLSIN
AGND
* PIN IN NC ON R6795-12
MD239F4 PO R6795 144T
)LJXUH 5 3LQ 74)3 3LQ 6LJQDOV
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RH56D-PCI Modem Designer's Guide
7DEOH 5 3LQ 74)3 3LQ 6LJQDOV
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Signal Label VIO VDD AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# VDD PAR CBE1# AD15 AD14 VDD AD13 AD12 AD11 AD10 VDD AD9 AD8 CBE0# VDD GND AD7 AD6 AD5 AD4 VDD AD3 AD2 AD1 AD0 DRESET# (GPOL0) SLEEPO (GPIO15) VSTROBE/NC VRXOUT/NC VSCLK/NC VTXSIN/NC VCLKIN/NC VCTRLSIN/NC IASLEEP AGND AGND
I/O Type PWR PWR I/Opts I/Opts I/Opts I/Opts PWR I/Opts I/Opts I/Opts I/Opts I/Opts I/Opsts I/Opsts I/Opsts I/Opsts I/Opsts I/Osts I/Opod PWR I/Opts I/Opts I/Opts I/Opts PWR I/Opts I/Opts I/Opts I/Opts PWR I/Opts I/Opts I/Opts PWR GND I/Opts I/Opts I/Opts I/Opts PWR I/Opts I/Opts I/Opts I/Opts Ot2 Ot12 OA OA OA IA IA IA DI GND GND
Interface3 PCI Bus: VI/O +3.3V PCI Bus: AD23 PCI Bus: AD22 PCI Bus: AD21 PCI Bus: AD20 +3.3V PCI Bus: AD19 PCI Bus: AD18 PCI Bus: AD17 PCI Bus: AD16 PCI Bus: CBE2# PCI Bus: FRAME# PCI Bus: IRDY# PCI Bus: TRDY# PCI Bus: DEVSEL# PCI Bus: STOP# PCI Bus: PERR# PCI Bus: SERR# +3.3V PCI Bus: PAR PCI Bus: CBE1# PCI Bus: AD15 PCI Bus: AD14 +3.3V PCI Bus: AD13 PCI Bus: AD12 PCI Bus: AD11 PCI Bus: AD10 +3.3V PCI Bus: AD9 PCI Bus: AD8 PCI Bus: CBE0# +3.3V GND PCI Bus: AD7 PCI Bus: AD6 PCI Bus: AD5 PCI Bus: AD4 +3.3V PCI Bus: AD3 PCI Bus: AD2 PCI Bus: AD1 PCI Bus: AD0 BIF: RESET# (68) R6795: IASLEEP R6795: V_STROBE (Note 3) R6795: V_RXOUT (Note 3) R6795: V_SCLK (Note 3) R6795: V_TXSIN (Note 3) R6795: M_CLK (Note 3) R6795: V_CTRL (Note 3) R6795: SLEEPO AGND AGND
Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Signal Label MCLKIN MTXSIN MSCLK MRXOUT MSTROBE AGND VDD SET3V# VDD XOUT XIN GND PME# V_CTRL V_TXSIN V_SCLK V_RXOUT V_STROBE M_STROBE M_RXOUT M_SCLK M_TXSIN M_CLK M_CTRL VDD GND GPIO14 SPKMUTE (GPIO8) GPIO3 VOICE# (GPIO2) CID# (GPIO1) OH# (GPIO0) VDD RINGWAKE# (INPUT0) INPUT1 LCS# (INPUT2) NC IRING# (INPUT3) EXT_L# (INPUT4) LCS_L#/RH_L# (INPUT5) GND VauxDET VDD VauxEN# VpciEN# GPOL1 SROMCS SROMOUT SROMIN SROMCLK INTA# PCIRST# VpciDET PCICLK GNT#
I/O Type IA IA OA OA OA GND PWR It PWR O I GND Ood Ot2 Ot It It It It It It Ot2 Ot2 Ot2 PWR GND Itpu/Ot12 It/Ot12 Itpu/Ot12 Ot12 Ot12 Ot12 PWR It Itpu Itpu
Interface R6795: M_CLK R6795: M_TXSIN R6795: M_SCLK R6795: M_RXOUT R6795: M_STROBE AGND +3.3V GND (+3.3V operation) or Open (+5V operation) +3.3V NC NC GND PCI Bus: PME# R6795: VCTRLSIN R6795: VTXSIN R6795: VSCLK R6795: VRXOUT R6795: VSTROBE R6795: MSTROBE R6795: MRXOUT R6795: MSCLK R6795: MTXSIN R6795: MCLKIN and VCLKIN R6795: MCTRLSIN +3.3V GND NC LAI: Speaker Control (output); Vaux Mode Power Select (input) NC LAI: Voice Relay Control LAI: Caller ID Relay Control LAI: Off-Hook Relay Control +3.3V +3.3V through 10K NC LAI: Handset Line Current Sense Output NC LAI: Ring Indicate LAI: Extension Off-hook Detector LAI: Line Current Sense/Remote Hang-up GND PCI Bus: VauxDET +3.3V Power Detection and Switching Ckt Power Detection and Switching Ckt NC SROM: Chip Select (CS) SROM: Data Out (DO) SROM: Data In (DI) SROM: Clock (SK) PCI Bus: INTA# PCI Bus: PCIRST# Power Detection and Switching Ckt PCI Bus: PCICLK PCI Bus: GNT#
Itpu Itpu Itpu GND Itpd PWR Ot2 Ot2 Ot2 Ot2 Itpu Ot4 Ot4 Opod Ip Itpd Ip Ipts
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RH56D-PCI Modem Designer's Guide
7DEOH 5 3LQ 74)3 3LQ 6LJQDOV &RQW*G
Pin 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Signal Label TELIN/NC AGNDV/NC TELOUT/NC AVDD SPKOUT TXA1 TXA2 VREF VC MIC_V/NC RXA AGNDM RESET# DSPKOUT AGND VDD MCTRLSIN
I/O Type I(DA) GND O(DD) PWR O(DF) O(DD) O(DD) REF REF I(DA) I(DA) GND It Ot2 GND PWR IA
Interface3 LAI: Handset Analog Output (Note 3) AGND (Note 3) LAI: Handset Analog Input (Note 3) VAA LAI: Speaker Analog Input LAI: Transmit Data Analog Input LAI: Transmit Data Analog Input VC through capacitors AGND through capacitors LAI: Microphone Output (Note 3) LAI: Received Data Output AGND BIF: DRESET# (45) LAI: Digital Speaker input AGND +3.3V R6795: M_CTRL
Pin 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Signal Label REQ# CLKRUN# AD31 AD30 AD29 AD28 AD27 VDD AD26 AD25 AD24 CBE3# VIO GND GND GND IDSEL
I/O Type Opts It I/Opts I/Opts I/Opts I/Opts I/Opts PWR I/Opts I/Opts I/Opts I/Opts PWR GND GND GND Ip
Interface PCI Bus: REQ# GND PCI Bus: AD31 PCI Bus: AD30 PCI Bus: AD29 PCI Bus: AD28 PCI Bus: AD27 +3.3V PCI Bus: AD26 PCI Bus: AD25 PCI Bus: AD24 PCI Bus: CBE3# PCI Bus: VI/O GND GND GND PCI Bus: IDSEL
Notes: 1. I/O types: I/Opod Input/Output, PCI, open drain (PCI type =o/d) I/Opsts Input/Output, PCI, sustained tristate (PCI type = s/t/s) I/Opts Input/Output, PCI, tristate (PCI type = t/s) Ip Input, PCI, totem pole (PCI type = in) Ipts Input, PCI, (PCI type = t/s) It Input, TTL Itpd Input, TTL, internal pull-down It/Ot Input, TTL/Output, TTL It/Ot12 Input, TTL/Output, TTL, 12 mA Ood Output, open drain Opod Output, PCI, open drain (PCI type =o/d) Opts Output, PCI, tristate (PCI type = t/s) Ot2 Output, TTL, 2 mA Ot12 Output, TTL, high =12 mA, low = -12 mA NC No internal connection. 2. Interface Legend: DAA Data Access Arrangement DB External Data Bus LAI Line/Audio Interface LVC Line/Voice Codec. NC No external connection. 3. This pin has no internal connection (NC) on R6793-12.
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RH56D-PCI Modem Designer's Guide
7DEOH 5 3LQ 6LJQDO 'HILQLWLRQV
Label
Pin
I/O Type SYSTEM
Signal Name/Description
XIN XOUT VDD
83 82 2, 7, 20, 25, 30, 34, 40, 71, 79, 81, 97, 105, 115, 135 59 35, 84, 98, 113, 141, 142, 143 54, 55, 70, 78 67 57 80 1 140 129
It, Ot2 PWR
Crystal In and Crystal Out. Connect XIN and XOUT to a 28.224000 MHz external crystal circuit. Digital Supply Voltage. Connect to +3.3V.
AVDD GND AGND AGNDM AGNDV SET3V# VIO VIO CLKRUN#
PWR GND GND GND GND It PWR Ip, (in, o/d, s/t/s) Ot2
Analog Circuits Digital Power. Connect to Analog IA power. Digital Ground. Connect to digital ground. Analog Ground. Connect to analog ground. Analog Ground Modem. Connect to analog ground. Analog Ground Voice. Connect to analog ground. Select 3.3V Analog Voltage Reference. Low selects +3.3V analog voltage reference; high selects +5V analog voltage reference I/O Signaling Voltage Source. Connect to PCI Bus VI/O. Used internally for PCI clamping. Clock Running. CLKRUN# is an input used to determine the status of CLK and an open drain output used to request starting or speeding up CLK. Connect to GND for PCI designs. May be connected to GND through 1K but resistor is not required. POWER DETECTION AND SWITCHING Vaux Enable. Active low output used to enable Vaux FET. For use in designs that switch between Vaux and Vpci for different power states and for retail designs where the target PC may or may not support Vaux. If used, tie to the gate of the P-FET connected between Vaux and board +3.3V grid. If not used, leave open. Vpci Enable. Active low output used to enable Vpci FET. For use in designs that switch between Vaux and Vpci for different power states and for retail designs where the target PC may or may not support Vaux. If used, tie to the gate of the P-FET connected between Vpci regulator output and board +3.3V grid. If not used, leave open. Vpci Detect. The VpciDET input indicates when PCI cycles and PCIRST# are to be ignored. Connect this pin to the PCI Bus +5V pins. VpciDET is deasserted when the PCI Bus enters the B3 state. If the +5V supply does not fall below 0.8V when in B3 state, a diode and resistor network may be incorporated to ensure VpciDET falls below 0.8V in order to be properly sensed by the BIF. This pin may alternatively be directly driven in embedded designs by using a logical signal, either +5V or +3.3V level, to indicate when the PCI Bus is in a B3 state. Driving this pin low synchronously to the PCI clock or when the PCI clock is stopped also allows the BIF to be put into a very low power mode, allowing system power consumption to be less than 20 mW. Therefore, using this method, if modem operation is not required, modem power consumption can be reduced even while the PCI Bus is in power state B0. SERIAL EEPROM INTERFACE
VauxEN#
116
VpciEN#
117
Ot2
VpciDET
125
Itpd
SROMCLK SROMCS SROMIN SROMOUT
122 119 121 120
Ot4 Ot2 Ot4 Itpu
Serial ROM Shift Clock. Connect to SROM SK input (frequency: 537.6 kHz). Serial ROM Chip Select. Connect to SROM CS input. Serial ROM Instruction, Address, and Data In. Connect to SROM DI input. Serial ROM Device Status and Data Out. Connect to SROM DO output, through 1k if using a +5V EEPROM.
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RH56D-PCI Modem Designer's Guide
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Label PCICLK PCIRST# AD[31:0] 126 124
Pin
I/O Type PCI BUS INTERFACE Ip (in) Ip (in) I/Opts (t/s)
Signal Name/Description PCI Bus Clock. The PCICLK (PCI Bus CLK signal) input provides timing for all transactions on PCI. Connect to PCI Bus: CLK. PCI Bus Reset. Active low input asserted to initialize PCI-specific registers, sequencers, and signals to a consistent reset state. Connect to PCI Bus: RST#. Multiplexed Address and Data. Address and Data are multiplexed on the same PCI pins. Connect to PCI Bus: AD[31-0].
130-134, 136138, 3-6, 8-11, 23-24, 26-29, 31-32, 36-39, 41-44 33 22 12 139 21
CBE0# CBE1# CBE2# CBE3# PAR
I/Opts (t/s)
Bus Command and Bus Enable. Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, CBE[3:0]# define the bus command. During the data phase, CBE[3:0]# are used as Byte Enables. Connect to PCI Bus: CBE[3:0]#. Parity. Parity is even parity across AD[31:00] and CBE[3:0]#. The master drives PAR for address and write data phases; the Bus Interface drives PAR for read data phases. Connect to PCI Bus: PAR. Cycle Frame. FRAME# is driven by the current master to indicate the beginning and duration of an access. Connect to PCI Bus: FRAME#. Initiator Ready. IRDY# is used to indicate the initiating agent's (bus master's) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. Connect to PCI Bus: IRDY#. Target Ready. TRDY# is used to indicate s the Bus Interface's ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. Connect to PCI Bus: TRDY#. Stop. STOP# is asserted to indicate the Bus Interface is requesting the master to stop the current transaction. Connect to PCI Bus: STOP#. Initialization Device. IDSEL input is used as a chip select during configuration read and write transactions. Connect to PCI Bus: IDSEL. Device Select. When actively driven, DEVSEL# indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. Connect to PCI Bus: DEVSEL#. Request. REQ# is used to indicate to the arbiter that this agent desires use of the bus. Connect to PCI Bus: REQ#. Grant. GNT# is used to indicate to the agent that access to the bus has been granted. Connect to PCI Bus: GNT#. Parity Error. PERR# is used for the reporting of data parity errors. Connect to PCI Bus: PERR#. System Error. SERR# is an open drain output asserted to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Connect to PCI Bus: SERR#. Interrupt A. INTA# is an open drain output asserted to request an interrupt. Connect to PCI Bus: INTA#. Power Management Event. Active low open drain or active high TTL output (selected by the PME DRV bit in the EEPROM) asserted when a valid ring signal is detected at the IRING# input and the PME_En bit of the PMCSR is a 1. This signal should be used only if the target PCI Bus supports power management wake-up event. Connect to the PCI Bus: PME#. Vaux Detect. Active high input used to detect the presence of Vaux. Connect to PCI Bus: Vaux. At device power on (POR), if D3_Cold bit in the EEPROM is a 1, PMC[15] is set to a 1 if VauxDET is high or PMC[15] is cleared to a 0 if VauxDET is low.
I/Opts (t/s) I/Opsts (s/t/s) I/Opsts (s/t/s) I/Opsts (s/t/s) I/Opsts (s/t/s) Ip (in) I/Opsts (s/t/s)
FRAME# IRDY#
13 14
TRDY#
15
STOP# IDSEL DEVSEL#
17 144 16
REQ# GNT# PERR# SERR#
128 127 18 19
I/Opts (t/s) I/Opts (t/s) I/Opsts (s/t/s) Ood (o/d) Ood (o/d) Opod (o/d)
INTA# PME#
123 85
VauxDET
114
Itpd
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RH56D-PCI Modem Designer's Guide
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Label
Pin
I/O Type
Signal Name/Description
TELEPHONE LINE (DAA)/AUDIO INTERFACE OH# (GPIO0) CID# (GPIO1) VOICE# (GPIO2) RINGWAKE# (INPUT 0) IRING# (INPUT3) LCS# (INPUT2) LCS_L#/RH_L# (INPUT 5) EXT_L# (INPUT4) SPKMUTE (GPIO8) 104 103 102 106 110 Ot12 Ot12 Ot12 It Itpu Off-Hook Relay Control. Output (typically active low) used to control the normally open off-hook relay. The polarity of this output is configurable. Caller ID Relay Control. Output (typically active low) used to control the normally open Caller ID relay. The polarity of this output is configurable. Voice Relay Control. Output (typically active low) used to control the normally open voice relay. The polarity of this output is configurable. Ring Wakeup. Not used. Connect to +3.3V through 10K . Ring Indicate. A low-going edge used to indicate presence of a ring frequency. Typically connected to the output of an optoisolator or equivalent. The idle state (no ringing) output of the ring detect circuit should be high. Line Current Sense Handset. Active low input used to indicate local modem handset off-hook status. Remote Hang-up. Active low input used to indicate hang-up of the remote modem or telephone, i.e., the remote modem/telephone has released the line (gone on-hook). Extension Offhook. Active low input used to indicate the telephone line is in use by the local handset or an extension phone. Speaker Mute/Vaux Mode Power Select. Output (typically active low) used to turn off (mute) the speaker during normal operation. Upon device reset, this pin is temporarily an input and is sampled. If sampled high and VauxDET is high, VpciEN# will be asserted when the device is in D0. If sampled low (e.g., SPKMUTE signal is pulled down to GND through 10k ) and VauxDET is high, VauxEN# will be asserted when the device is in D0. VauxEN# is always asserted when VauxDET is high in D3 with PME enabled. Either VauxEN# or VpciEN#, but not both, can be asserted at the same time. RXA TXA1 TXA2 SPKOUT 66 61 62 60 I(DA) O(DF) O(DF) Receive Analog. RXA is a single-ended receive data input from the telephone line interface or an optional external hybrid circuit. The input impedance is > 70k . Transmit Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other. Each output can drive a 300 load. Modem Speaker Analog Output. The SPKROUT_M analog output reflects the received analog input signal. The SPKROUT_M on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the SPKROUT_M output is clamped to the voltage at the VC pin. The SPKROUT_M output can drive an impedance as low as 300 ohms. In a typical application, the SPKROUT_M output is an input to an external LM386 audio power amplifier. Modem Speaker Digital Output. The DSPKOUT digital output reflects the received analog input signal digitized to TTL high or low level by an internal comparator to create a PC Card (PCMCIA)-compatible signal.
108 112 111 100
Itpu Itpu Itpu It/Ot12
DSPKOUT
69
OA
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RH56D-PCI Modem Designer's Guide
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Label TELOUT/NC 58
Pin
I/O Type O(DF)
Signal Name/Description Telephone Handset Analog Output (R6793-12)/NC (R6793-11). R6793-12: TELOUT is a single-ended analog output to the telephone handset speaker interface circuit. TELOUT can drive a 300 load. R6793-11: NC pin can be left open, or connected as for R6793-12 without signal support.
TELEPHONE LINE (DAA)/AUDIO INTERFACE (CONTINUED)
TELIN/NC
56
I(DA)
Telephone Handset Analog Input R6793-12)/NC (R6793-11). R6793-12: TELIN is a single-ended analog input from the telephone handset microphone interface circuit. The input impedance is > 70k . R6793-11: NC pin can be left open, or connected as for R6793-12, without signal support.
MIC_V/NC
65
I(DA)
Voice Microphone Input (R6793-12)/NC (R6793-11). R6793-12: MIC_V is a single-ended microphone input. The input impedance is > 70k . R6793-11: NC pin can be left open, or connected as for R6793-12 without signal support.
VREF
63
REF
High Voltage Reference. Connect to VC through 10 F (polarized, + terminal to VREF) and 0.1 F (ceramic) in parallel. Ensure a very close proximity between these capacitors and VREF pin. Low Voltage Reference. Connect to analog ground through 10 F (polarized, + terminal to VC) and 0.1 F (ceramic) in parallel. Ensure a very close proximity between these capacitors and VC pin. Use a short path and a wide trace to AGND pin. R6795 INTERCONNECT/NO CONNECT Connect to R6795: IASLEEP. Connect to R6795: SLEEPO. Connect to R6795: MCLKIN and VCLKIN. R6795-12: Connection to VCLKIN is not required, but may be done to common board design. Connect to R6795: MSCLK. Connect to R6795: MSTROBE. Connect to R6795: MTXSIN. Connect to R6795: MRXOUT. Connect to R6795: MCTRLSIN. Connect to R6795: M_CLK. Connect to R6795: M_SCLK. Connect to R6795: M_STROBE. Connect to R6795: M_TXSIN. Connect to R6795: M_RXOUT. Connect to R6795: M_CTRL.
VC
64
REF
SLEEPO (GPIO15) IASLEEP M_CLK M_SCLK M_STROBE M_TXSIN M_RXOUT M_CTRL MCLKIN MSCLK MSTROBE MTXSIN MRXOUT MCTRLSIN
46 53 95 93 91 94 92 96 73 75 77 74 76 72
Ot12 DI Ot2 It It Ot2 It Ot2 IA OA OA IA OA IA
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RH56D-PCI Modem Designer's Guide
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Label V_SCLK V_STROBE V_TXSIN V_RXOUT V_CTRL VCLKIN/NC VSCLK/NC VSTROBE/NC VTXSIN/NC VRXOUT/NC VCTRLSIN/NC 88 90 87 89 86 51 49 47 50 48 52
Pin It It
I/O Type
Signal Name/Description R6795-11: Connect to R6795: VSCLK. R6795-12: This pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: VSTROBE. R6795-12: This pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: VTXSIN. R6795-12: This pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: VRXOUT. R6795-12: This pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: VCTRLSIN. R6795-12: This pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: M_CLK. R6795-12: NC pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: V_SCLK. R6795-12: NC pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: V_STROBE. R6795-12: NC pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: V_TXSIN. R6795-12: NC pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: V_RXOUT. R6795-12: NC pin may be left open or connected as for R6795-11. R6795-11: Connect to R6795: V_CTRL. R6795-12: NC pin may be left open or connected as for R6795-11. NOT USED General Purpose Output. NC. General Purpose Input/Output. NC. General Purpose Input/Output. NC. General Purpose Input. NC. Modem Reset. Connect to BIF: RESET# (pin 68). DSP Reset. Connect to BIF: DRESET# (pin 45). NC.
Ot It Ot2 IA OA OA IA OA IA
GPOL1 GPIO3 GPIO14 INPUT1 DRESET# (GPOLl0) RESET# NC
118 101 99 107 45 68 109
Ot2 Itpu/Ot12 Itpu/Ot12 Itpu Ot2 IA NC
Notes: 1. I/O types: I/Opod Input/Output, PCI, open drain (PCI type =o/d) I/Opsts Input/Output, PCI, sustained tristate (PCI type = s/t/s) I/Opts Input/Output, PCI, tristate (PCI type = t/s) Ip Input, PCI, totem pole (PCI type = in) Ipts Input, PCI, (PCI type = t/s) It Input, TTL Itpd Input, TTL, internal pull-down It/Ot Input, TTL/Output, TTL It/Ot12 Input, TTL/Output, TTL, 12 mA Ood Output, open drain Opod Output, PCI, open drain (PCI type =o/d) Opts Output, PCI, tristate (PCI type = t/s) Ot2 Output, TTL, 2 mA Ot12 Output, TTL, high =12 mA, low = -12 mA NC No internal connection. 2. Interface Legend: DAA Data Access Arrangement DB External Data Bus LAI Line/Audio Interface LVC Line/Voice Codec NC No external connection.
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RH56D-PCI Modem Designer's Guide
VCC D1 BAS16 R12 10K +3.3V
2 7 20 25 30 34 40 81 97 105
115
135
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD
PCIPME# VI/O VAUX
PCIPME#
85 1 140 114 117 116 125 118
VDD
U3 SROMCS SROMCLK SROMIN SROMOUT 119 122 121 120 104 103 102 101 100 99 46 95 88 93 90 91 87 94 89 92 86 96 72 52 76 48 74 50 77 47 75 49 73 51 53 68 69 60 65 61 62 66 63 64 56 58 59 71 79 54 55 70 78 57 67 80 109 R16 Not Installed = +5V IA Operation R 1 6 R16 Installed = +3.3V IA Operation 0 ANALOG_IA_POWER +3.3V C30 0.1uF + C31 10uF DRESET# DSPKOUT DSPKOUT SPKOUT MIC_V TXA1 TXA2 RXA SROMCS SROMCLK SROMIN SROMOUT R10 OH# 1 2 3 4 1k OH# CS SK DI DO GND PE PRE VDD 5 6 7 8
PME# VIO1 VIO2
EEPROMVCC
INPUT7/VauxDET GPOH1/VpciEN GPOH0/VauxEN VpciDET GPOL1 PCICLK CLKRUN# PCIRST# FRAME# IDSEL DEVSEL# IRDY# TRDY# CBE0# CBE1# CBE2# CBE3# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PAR REQ# GNT# INTA# STOP# PERR# SERR# INPUT5/LCS_L#/RH_L# INPUT4/EXT_L# INPUT3/IRING# INPUT2/LCS# INPUT1 INPUT0/RINGWAKE# GPOL0/DRESET# SDXTAL1/XIN SDXTAL2/XOUT GND GND GND GND GND GND GND
PCICLK PCIRESET# FRAME# IDSEL DEVSEL# IRDY# TRDY# C/BE0# C/BE1# C/BE2# C/BE3# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCICLK PCIRESET# FRAME# IDSEL DEVSEL# IRDY# TRDY# C/BE0# C/BE1# C/BE2# C/BE3#
126 129 124 13 144 16 14 15 33 22 12 139 44 43 42 41 39 38 37 36 32 31 29 28 27 26 24 23 11 10 9 8 6 5 4 3 138 137 136 134 133 132 131 130
OH#/GPIO0 CID#/GPIO1 VOICE#/GPIO2 GPIO3 GPIO8 RESETEN/GPIO14 SLEEPO/GPIO15 M_CLK V_SCLK M_SCLK V_STROBE M_STROBE V_TXSIN M_TXSIN V_RXOUT M_RXOUT V_CTRL M_CTRL MCTRLSIN VCTRLSIN MRXOUT VRXOUT MTXSIN VTXSIN MSTROBE VSTROBE MSCK VSCK MCLKIN VCLKIN IASLEEP RESET# DSPKOUT SPKOUT MIC_V TXA1 TXA2 RXA VREF VC TELIN TELOUT AVDD VDD VDD AGND AGND AGND AGND AGNDV AGNDM SET3V# NC
NM93C66M8
SPEAKMUTE IASLEEP M_CLK V_SCLK M_SCLK V_STROBE M_STROBE V_TXSIN M_TXSIN V_RXOUT M_RXOUT V_CTRL M_CTRL
SPEAKMUTE
R6795
AD[0..31]
TXA1 TXA2 RXA VREF VC C28 0.1uF
VCC
PAR REQ# GNT# INTA# STOP# PERR# SERR#
PAR REQ# GNT# INTA# STOP# PERR# SERR#
21 128 127 123 17 18 19 112 111 110 108 107 106 45 83 82
+ C29 10uF
10K IRING#
IRING# RINGWAKE# DRESET#
L2
Ferrite For Layout: Place Vref and VC Components near U7 (R6793)
C32 27pF 5% Y1 28.224MHz C33 27pF 5% IN1 INSULATOR for Y1 R15 1M
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RH56D-PCI Modem Designer's Guide
3.2 POWER REQUIREMENTS AND MAXIMUM RATINGS
The current and power requirements are listed in Table 3-3. The absolute maximum ratings are listed in Table 3-4.
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Conditions Device State (Dx) and Bus State (Bx) D0, B0 D0, B0 D3, B0 D3, B1 D3, B2, B3 (D3 hot) D3, B3 (D3 cold) Notes: PCI Bus Power On On On On On Off PCI Clock (PCICLK) Running Running Running Running Stopped Stopped Line Connection Yes No No No No No
Current Typical Current (mA) TBD TBD TBD TBD TBD TBD Maximum Current (mA) TBD TBD TBD TBD TBD TBD
Power Typical Power (mW) TBD TBD TBD TBD TBD TBD Maximum Power (mW) TBD TBD TBD TBD TBD TBD
Operating voltage: VDD = +3.3V 0.3V. Test conditions: VDD = +3.3 VDC for typical values; VDD = +3.6 VDC for maximum values. Definitions: PCI Bus Power On: PCI Bus +5V and +3.3V on (modem normally powered by +3.3V from PCI Bus +3.3V or regulated down from PCI Bus +5V); PCIRST# not asserted. Off: PCI Bus +5V and +3.3V off (modem normally powered by +3.3V from Vaux or Vpci); PCIRST# asserted. PCI Clock (PCICLK) Running: PCI Bus signal PCICLK running; Stopped: PCI Bus signal PCICLK stopped (off). Line connection: Yes: Off-hook, IA powered. No: On-hook, IA powered down. Device States: D3: Low power state. Suspend state can change the system power state; the resulting power state depends on the system architecture (OS, BIOS, hardware) and system configuration (i.e., other PCI installed cards). D0: Full power state. Device and Bus States: D0, B0: Any PCI transaction, PCICLK running, VCC present. D3, B1: No PCI Bus transactions, PCICLK running, VCC present. D3, B2, B3: No PCI transactions, PCICLK stopped, VCC may be present. D3, B3: No PCI transactions, PCICLK stopped, no VCC. Refer to the PCI Bus Power Management Interface Specification for additional information.
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Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Analog Inputs Voltage Applied to Outputs in High Impedance (Off) State DC Input Clamp Current DC Output Clamp Current Static Discharge Voltage (25C) Latch-up Current (25C) * VIO = +3.3V 0.3V or +5V 5%.
Symbol VDD VIN TA TSTG VIN VHZ IIK IOK VESD ITRIG
Limits -0.5 to +4.0 -0.5 to (VIO +0.5)* -0 to +70 -55 to +125 -0.3 to (VAA + 0.5) -0.5 to (VIO +0.5)* 20 20 2500 400
Units V V C C V V mA mA V mA
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RH56D-PCI Modem Designer's Guide
3.3 MDP ELECTRICAL CHARACTERISTICS
The MDP analog electrical characteristics for the hardware interface signals are listed in Table 3-5.
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Signal Name RIN, TELIN, MIC_V TXA1, TXA2, TELOUT
Type I (DA)
Characteristic Input Impedance AC Input Voltage Range Reference Voltage Minimum Load Maximum Capacitive Load Output Impedance AC Output Voltage Range Reference Voltage DC Offset Voltage
Value > 70K 1.1 VP-P +1.35 VDC (VAA = +3.3V) or +2.5 VDC (VAA = +5V) 300 0 F 10 1.4 VP-P (VAA = +3.3V) or 2.2 VP-P (VAA = +5V) (with reference to ground and a 600 load) +1.35 VDC (VAA = +3.3V) or +2.5 VDC (VAA = +5V) 200 mV 300 0.01 F 10 1.4 VP-P (VAA = +3.3V) or 2.2 VP-P (VAA = +5V) +1.35 VDC (VAA = +3.3V) or +2.5 VDC (VAA = +5V) 20 mV
O (DD)
SPKOUT
O (DF)
Minimum Load Maximum Capacitive Load Output Impedance AC Output Voltage Range Reference Voltage DC Offset Voltage
3.4 PCI BUS ELECTRICAL, SWITCHING, AND TIMING CHARACTERISTICS
The PCI Bus electrical, switching, and timing characteristics conform to the PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995.
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RH56D-PCI Modem Designer's Guide 4. DESIGN CONSIDERATIONS
Good engineering practices must be followed when designing a printed circuit board (PCB) containing the modem device. This is especially important considering the high data bit rate, high fax rate, record/play of analog speech and music audio, and full-duplex speakerphone operation. Suppression of noise is essential to the proper operation and performance of the modem and interfacing audio and DAA circuits. Two aspects of noise in an OEM board design containing the modem device set must be considered: on-board/off-board generated noise that can affect analog signal levels and analog-to-digital conversion (ADC)/digital-to-analog conversion (DAC), and on-board generated noise that can radiate off-board. Both on-board and off-board generated noise that is coupled on-board can affect interfacing signal levels and quality, especially in low level analog signals. Of particular concern is noise in frequency ranges affecting modem and audio circuit performance. On-board generated electromagnetic interference (EMI) noise that can be radiated or conducted off-board is a separate, but equally important, concern. This noise can affect the operation of surrounding equipment. Most local governing agencies have stringent certification requirements that must be met for use in specific environments. In order to minimize the contribution of the circuit design and PCB layout to EMI, the designer must understand the major sources of EMI and how to reduce them to acceptable levels. Proper PC board layout (component placement and orientation, signal routing, trace thickness and geometry, etc.), component selection (composition, value, and tolerance), interface connections, and shielding are required for the board design to achieve desired modem performance and to attain EMI certification. In addition, design layout should meet requirements stated in the PCI Bus Specification, Section 4.4, Expansion Board Specification, as well as other applicable sections. All the aspects of proper engineering practices are beyond the scope of this designer's guide. The designer should consult noise suppression techniques described in technical publications and journals, electronics and electrical engineering text books, and component supplier application notes. Seminars addressing noise suppression techniques are often offered by technical and professional associations as well as component suppliers. The following guidelines are offered to specifically help achieve stated modem performance, minimize audible noise for audio circuit use, and to minimize EMI generation.
4.1 PC BOARD LAYOUT GUIDELINES
4.1.1 General Principles 1. 2. 3. 4. 5. 6. 7. 8. Provide separate digital, analog, and DAA sections on the board. Keep digital and analog components and their corresponding traces as separate as possible and confined to defined sections. Keep high speed digital traces as short as possible. Keep sensitive analog traces as short as possible. Provide proper power supply distribution, grounding, and decoupling. Provide separate digital ground, analog ground, and chassis ground (if appropriate) planes. Provide wide traces for power and critical signals. Position digital circuits near the host bus connection and position the DAA circuits near the telephone line connections.
4.1.2 Component Placement 1. From the system circuit schematic, a) b) c) 2. Identify the digital, analog, and DAA circuits and their components, as well as external signal and power connections. Identify the digital, analog, mixed digital/analog components within their respective circuits. Note the location of power and signals pins for each device (IC).
Roughly position digital, analog, and DAA circuits on separate sections of the board. Keep the digital and analog components and their corresponding traces as separate as possible and confined to their respective sections on the board. Typically, the digital circuits will cover one-half of the board, analog circuits will cover one-fourth of the board, and the DAA will cover one-fourth of the board. NOTE: While the DAA is primarily analog in nature, it also has many control
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RH56D-PCI Modem Designer's Guide
and status signals routed through it. A DAA section is also governed by local government regulations covering subjects such as component spacing, high voltage suppression, and current limiting. 3. Once sections have been roughly defined, place the components starting with the connectors and jacks. a) b) c) 4. Allow sufficient clearance around connectors and jacks for mating connectors and plugs. Allow sufficient clearance around components for power and ground traces. Allow sufficient clearance around sockets to allow the use of component extractors.
First, place the mixed analog/digital components (e.g., modem device, A/D converter, and D/A converter). a) b) Orient the components so pins carrying digital signals extend onto the digital section and pins carrying analog signals extend onto the analog section as much as possible. Position the components to straddle the border between analog and digital sections.
5.
Place all analog components. a) b) c) Place the analog circuitry, including the DAA, on the same area of the PCB. Place the analog components close to and on the side of board containing the TXA1, TXA2, RXA, VC, and VREF signals. Avoid placing noisy components and traces near TXA1, TXA2, RXA, VC, and VREF lines.
6.
Place active digital components/circuits and decoupling capacitors. a) b) c) d) Place digital components close together in order to minimize signal trace length. Place 0.1 F decoupling (bypass) capacitors close to the pins (usually power and ground) of the IC they are decoupling. Make the smallest loop area possible between the capacitor and power/ground pins to reduce EMI. Place host bus interface components close to the edge connector in accordance with the applicable bus interface standard, e.g., the PCI Bus Specification. Place crystal circuits as close as possible to the devices they drive.
7.
Provide a "connector" component, usually a zero ohm resistor or a ferrite bead at one or more points on the PCB to connect one section's ground to another.
4.1.3 Signal Routing 1. 2. Route the modem signals to provide maximum isolation between noise sources and noise sensitive inputs. When layout requirements necessitate routing these signals together, they should be separated by neutral signals. Keep digital signals within the digital section and analog signals within the analog section. (Previous placement of isolation traces should prevent these traces from straying outside their respective sections.) Route the digital traces perpendicular to the analog traces to minimize signal cross coupling. Provide isolation traces (usually ground traces) to ensure that analog signals are confined to the analog section and digital traces remain out of the analog section. A trace may have to be narrowed to route it though a mixed analog/digital IC, but try to keep the trace continuous. a) b) 4. 5. 6. 7. 8. 9. Route an analog isolation ground trace, at least 50 mil to 100 mil wide, around the border of the analog section; put on both sides of the PCB. Route a digital isolation ground trace, at least 50 mil to 100 mil wide, and 200 mil wide on one side of the PCB edge, around the border of the digital section.
3.
Keep host interface signals (e.g., AEN, IOR#, IOW#, HRESET) traces at least 10 mil thick (preferably 12 - 15 mil). Keep analog signal (e.g., the TXA1, TXA2, RXA, TELIN, TELOUT, MIC_V, and SPKOUT) traces at least 10 mil thick (preferably 12 - 15 mil). Keep all other signal traces as wide as possible, at least 5 mil (preferably 10 mil). Route the signals between components by the shortest possible path (the components should have been previously placed to allow this). Route the traces between bypass capacitors to IC pins, at least 25 mil wide; avoid vias if possible. Gather signals that pass between sections (typically low speed control and status signals) together and route them between sections through a path in the isolation ground traces at one (preferred) or two points only. If the path is made
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on one side only, then the isolation trace can be kept contiguous by briefly passing it to the other side of the PCB to jump over the signal traces. 10. Avoid right angle (90 degree) turns on high frequency traces. Use smoothed radiuses or 45 degree corners. 11. Minimize the number of through-hole connections (feedthroughs/vias) on traces carrying high frequency signals. 12. Keep all signal traces away from crystal circuits. 13. Distribute high frequency signals continuously on a single trace rather than several traces radiating from one point. 14. Provide adequate clearance (e.g., 60 mil minimum) around feedthroughs in any internal planes in the DAA circuit. 15. Eliminate ground loops, which are unexpected current return paths to the power source. 16. Route PCICLK in accordance with Section 4.2.3. 4.1.4 Power 1. 2. Identify digital power (VDD) and analog power (AVDD) supply connections. Place a 10 F electrolytic or tantalum capacitor in parallel with a ceramic 0.1 F capacitor between power and ground at one or more points in the digital section. Place one set nearest to where power enters the PCB (edge connector or power connector) and place another set at the furthest distance from where power enters the PCB. These capacitors help to supply current surge demands by the digital circuits and prevent those surges from generating noise on the power lines that may affect other circuits. For 2-layer boards, route a 200-mil wide power trace on two edges of the same side of the PCB around the border of the circuits using the power. (Note that a digital ground trace should likewise be routed on the other side of the board.) Generally, route all power traces before signal traces.
3. 4.
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4.1.5 Ground Planes 1. In a 2-layer design, provide digital and analog ground plane areas in all unused space around and under digital and analog circuit components (exclusive of the DAA), respective, on both sides of the board, and connect them such a manner as to avoid small islands. Connect each ground plane area to like ground plane areas on the same side at several points and to like ground plane areas on the opposite side through the board at several points. Connect all modem GND pins to the digital ground plane area and AGND pins to the analog ground plane area. Typically, separate the collective digital ground plane area from the collective analog ground plane area by a fairly straight gap. There should be no inroads of digital ground plane area extending into the analog ground plane area or visa versa. In a 4-layer design, provide separate digital and analog ground planes covering the corresponding digital and analog circuits (exclusive of the DAA), respectively. Connect all modem GND pins to the digital ground plane and AGND pins to the analog ground plane. Typically, separate the digital ground plane from the analog ground plane by a fairly straight gap. In a design which needs EMI filtering, define an additional "chassis" section adjacent to the bracket end of a plug-in card. Most EMI components (usually ferrite beads/capacitor combinations) can be positioned in this section. Fill the unused space with a chassis ground plane, and connect it to the metal card bracket and any connector shields/grounds. Keep the current paths of separate board functions isolated, thereby reducing the current's travel distance. Separate board functions are: host interface, display, digital (SRAM, EPROM, modem), and DAA. Power and ground for each of these functions should be separate islands connected together at the power and ground source points only. Connect grounds together at only one point, if possible, using a ferrite bead. Allow other points for grounds to be connected together if necessary for EMI suppression. Keep all ground traces as wide as possible, at least 25 mil to 50 mil. Keep the traces connecting all decoupling capacitors to power and ground at their respective ICs as short and as direct (i.e., not going through vias) as possible.
2.
3.
4.
5. 6. 7.
4.1.6 Crystal Circuit 1. Keep all traces and component leads connected to crystal input and output pins (i.e., XTLI and XTLO) short in order to reduce induced noise levels and minimize any stray capacitance that could affect the crystal oscillator. Keep the XTLO trace extremely short with no bends greater than 45 degrees and containing no vias since the XTLO pin is connected to a fast rise time, high current driver. Where a ground plane is not available, such as in a 2-layer design, tie the crystal capacitors ground paths using separate short traces (as wide as possible) with minimum angles and vias directly to the corresponding device digital ground pin nearest the crystal pins. Connect crystal cases(s) to ground (if applicable). Place a 100-ohm (typical) resistor between the XTLO pin and the crystal/capacitor node. Connect crystal capacitor ground connections directly to GND pin on the modem device. Do not use common ground plane or ground trace to route the capacitor GND pin to the corresponding modem GND pin.
2.
3. 4. 5.
4.1.7 VC and VREF Circuit 1. Provide extremely short, independent paths for VC and VREF capacitor connections. a) Route the connection from the plus terminal of the 10 F VC capacitor and one terminal of the 0.1 F VC capacitor to the modem device VC pin using a single trace isolated from the trace to the VC pin from the VREF capacitors (see step d). Route the connection from the negative terminal of the 10 F VC capacitor and the other terminal of a the 0.1 F VC capacitor to a ferrite bead. The bead should typically have characteristics such as: impedance = 70 at a frequency of 100 MHz, rated current = 200 mA, and maximum resistance = 0.5 . Connect the other bead terminal to an AGND pin with a single trace. Route the connection from the plus terminal of the 10 F VREF capacitor and one terminal of the 0.1 F VREF capacitor to the modem device VREF pin with a single trace. Route the connection from the negative terminal of 10 F VREF capacitor and the other terminal of the 0.1 F VREF capacitor to the modem device VC pin with a single trace isolated from the trace to the VC pin from the VC capacitors (see step a).
b)
c) d)
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4.1.8 Telephone and Local Handset Interface 1. 2. Place common mode chokes in series with Tip and Ring for each connector. Decouple the telephone line cables at the telephone line jacks. Typically, use a combination of series inductors, common mode chokes, and shunt capacitors. Methods to decouple telephone lines are similar to decoupling power lines, however, telephone line decoupling may be more difficult and deserves additional attention. A commonly used design aid is to place footprints for these components and populate as necessary during performance/EMI testing and certification. Place high voltage filter capacitors (.001 F @1KV) from Tip and Ring to digital ground.
3.
4.1.9 Optional Configurations Because fixed requirements of a design may alter EMI performance, guidelines that work in one case may deliver little or no performance enhancement in another. Initial board design should, therefore, include flexibility to allow evaluation of optional configurations. These optional configurations may include: 1. 2. 3. Chokes in Tip and Ring lines replaced with jumper wires as a cost reduction if the design has sufficient EMI margin. Various grounding areas connected by tie points (these tie points can be short jumper wires, solder bridges between close traces, etc.). Develop two designs in parallel; one based on a 2-layer board and the other based on a 4-layer board. During the evaluation phase, better performance of one design over another may result in quicker time to market.
4.1.10 MDP Specific 1. 2. 3. 4. 5. Locate the MDP device and all supporting analog circuitry, including the data access arrangement, on the same area of the PCB. Locate the analog components close to and on the side of board containing the TXA1, TXA2, RXA, TELIN, TELOUT, MIC_V, and SPKOUT signals. Avoid placing noisy components and traces near the TXA1, TXA2, RXA, TELIN, TELOUT, MIC_V, and SPKOUT lines. Route MDP modem interconnect signals by the shortest possible route avoiding all analog components. Provide an RC network on the AVAA supply in the immediate proximity of the AVAA pin to filter out high frequency noise above 115 kHz. A tantalum capacitor is recommended (especially in a 2-layer board design) for improved noise immunity with a current limiting series resistor or inductor to the VCC supply which meets the RC filter frequency requirements. Provide a 0.1 F ceramic decoupling capacitor to ground between the high frequency filter and the VAA pin. Provide a 0.1 F ceramic decoupling capacitor to ground between the VCC supply and the AVDD pin.
6. 7.
4.2 CUSTOM DESIGN GUIDELINES FOR 2-LAYER PCI MODEM BOARD
Purpose of this section is to provide additional design guidelines customized for PCI boards utilizing only two layers. For a complete summary of PCB design guidelines, refer to the Section 4.1. 4.2.1 General Guidelines 1. 2. 3. 4. 5. 6. 7. 8. 9. Tie separate ground planes together at only one point. Fill bare board areas (top and bottom) with ground or Vcc (use 50-50 ratio or favor ground). Provide 15 to 40 mil spacing between analog and digital ground traces. Provide 25 mil minimum width for power and ground traces. Provide 15 mil minimum width for crystal traces. Avoid inconsistencies in routing; EMI radiation will occur every time a trace changes it's impedance. Prevent turns greater than 45 degrees. Prevent different thickness on a trace. Apply ground fill under crystals.
10. Follow the examples illustrated in Section 4.3.
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RH56D-PCI Modem Designer's Guide
4.2.2 Placement of Modem Devices 1. 2. 3. Rotate and position the Modem devices to minimize the number of vias on all traces. Rotate and position the device with the PCI interface to minimize trace lengths of PCI signals. Rotate and position the device with the analog interface the analog section is separated from the PCI area and other fast signals.
4.2.3 Trace Routing and Length on PCI Signals 1. The modem device pinouts are arranged such that signal routing to the PCI connector can be done with at most one via. If any signals cross, the net-list is wrong. The essential rules are: consistent trace aperture, minimum number of vias, trace bends at 45 degree angle maximum. Provide 15 mils minimum trace widths for the PCICLK, MRXCLK, MTXCLK, MPLLOUT, BIT_CLK clock signals. Keep the trace widths as consistent as possible to minimize impedance changes. This also means that the trace going into a series terminating resistor should the same on both sides. No vias are permitted on the clock-carrying traces. Clocks should always be routed on one side of the board. PCI 2.1 specification puts a strict length limit on PCI signals. The PCICLK trace must be 2.5 0.1" in length; other PCI signal traces should be less than 1.5" in length. Conexant reference designs achieve the required length by performing a zigzag routing with (a) rounded corners for lower EMI and (b) approximately double width traces compared to other PCI interface signals for lower impedance/EMI. The PCICLK signal is one of the largest sources of EMI on PCI peripheral designs. Surround this trace on both sides by guard-bands of digital ground that envelope PCICLK along the entire length. This technique also aims at approximating the required impedance relationship of PCICLK with respect to ground distribution. Connect this guard-band to ground pins immediately next to the PCICLK pin at the PCI connector. . Also, see Section 4.1.3. Provide guard-band also for the OSC_OUT clock trace. Decouple guard-band with a surface mount capacitors.
2.
3.
4.
5.
4.2.4 Grounding Because EMI always takes the easiest path to earth ground, ensure that EMI has no problem finding it in a harmless way. 1. Provide ground paths to the bracket. The best ground is provided by the bracket, not by the ground pins on the bus (while the ground pins provide effective signal returns to the motherboard, at high frequencies these traces become inductors that acquire higher impedance with increasing frequency). The bracket ground which connects to the chassis is quite beneficial in dealing with unwanted EMI. This includes using both bracket screws with as much contact surface area as possible to ground (including under the screw head), and pin 1 on any audio connectors (which tie to the bracket via the connector chassis and screw). On the bracket edge of the board, place a ground strip on both sides of the board. The bracket ground (chassis ground) depends on the PC's case, so choose a system for FCC testing with good EMI shielding. Experience has shown different PC brands can have quite different EMI characteristics of their own. Surround noisy signals, especially clocks, with a guard-band of thick traces of ground. Pay special attention to where the guard-bands are grounded, as the effectiveness of this technique will be greatly diminished with the increased physical distance. When vias must be used on traces with power/ground distribution, use multiple vias rather than a single via. The more vias, the lower the impedance. Avoid vias on traces carrying fast signals at any cost. Every place the impedance on a trace changes an additional EMI is generated. RipTide device signals are designed to route to the PCI connector and codec without signal crossover. Therefore, there should be very little need for vias. PCI signals on the blank side of the board should have only one via. Other PCI signals should have no vias. If radiated emissions move 6 or more dBuV just by slightly moving connected cables, the grounding technique used in design should be improved. At this point, maximize dumping EMI energy directly to the bracket ground without dumping too much EMI energy to scattered ground traces on the board.
2.
3. 4.
5.
4.2.5 Filtering 1. A general rule of thumb is to filter every connector on the board. On audio combo boards, these filters take the form of ferrite beads and capacitors. Place a ferrite in series with the signal and a capacitor between the signal and ground. After the signal is filtered, it must not be exposed to any board noise. Therefore, the filter must be as close to the connector as possible and filtered signals kept away from the digital ground and power.
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2. On some designs, place a ferrite between bracket ground and digital ground. This helps keep digital noise away from the connector but has the harmful side effect of making the digital area of the board noisier.
4.2.6 Decoupling 1. Another way to deal with EMI is to short it to ground through proper decoupling capacitors (caps). Because traces and component leads become inductors at high frequencies, use surface mount caps if possible, and place them close to the device being decoupled. Decouple power pins of a device directly to associated ground pins of the device between traces as close to the device as possible, i.e., not to a remote ground plane. If you have power and ground planes, connect capacitors to the planes with more than one via. This will decrease the lead inductance and increase the effectiveness of the capacitors. Capacitors are useful in reducing EMI is that they provide a high frequency short to ground. This is good if the ground plane is properly grounded (i.e., short path to chassis ground.), However if the ground plane isn't properly grounded, then the decoupling caps need to be used to source as much noise to the ground plane as it can handle. Also note that the desired value of the decoupling cap depends on the frequency that you want to eliminate. With higher system clock rates it is necessary to have a mixture of values for decoupling caps (e.g., 0.001 uF, 0.01 uF and 0.1 uF). Sourcing too much energy to ground can be just as harmful EMI-wise as not sourcing enough should the path to ground be poor. The capacitor value chosen for the offending frequency can be mathematically correct but also cause excessive EMI ripple on the ground. Unless the impedance of ground traces can be reduced, the solution is to reduce the capacitor value. As an example, if the board is excessively radiating at 100 MHz with a 0.01 uF cap, try a 0.047. The idea is to only source as much energy to ground as the ground can handle, no more or it will radiate.
2.
3.
Capacitor Value 0.1 uF 0.01 uF 0.001 uF
Frequency of Reduced EMI 10 MHz 30 MHz 100 MHz
4.
There is some overlap, as these values will change as inductance of the board comes into effect, and the fact you rarely have just one frequency to contend with. Another rule of thumb, derived from experiences, is 0.1 uF for <80 MHz, 0.01 uF for 60-500 MHz, and 0.001 uF for >400 MHz. The designer should provide several different values for de-coupling capacitors. These should be spread evenly around the power pins of devices on the board. A few capacitors can be placed in open areas of the board to stabilize the power and ground. Separate analog power/ground from digital power/ground with inductors or ferrite beads. The side effect of this separation is that the analog circuit cannot dump their high frequency noise to the chassis ground. The EMI characteristic of boards can be improved by using adequate decoupling and by limiting the areas of analog power/ground. The de-coupler on the PCICLK guard-band should be 0.001 uF to handle the clock harmonics. Decouple this guard-band directly to a VCC pin near the PCICLK pin at the PCI connector. Provide several different values for de-coupling capacitors. These should be spread evenly around the power pins of devices on the board. A few caps can be placed in open areas of the board to stabilize the power and ground.
5.
6. 7.
4.2.7 Crystal Circuit 1. Provide a separate trace(s) for the ground connections of the crystal's bypass capacitors going back to the digital ground pins of the modem device(s). These traces should be as short as possible, relatively thick, and have minimal sharp bends. Avoid tying the ground connections of these capacitors to surrounding ground copper island(s). In these cases, the return high-frequency currents do not necessarily choose the shortest path and instead, they ripple the surrounding ground distribution with EMI. Lay the crystal flat against a ground plane that has a low impedance path to ground.
2.
3.
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RH56D-PCI Modem Designer's Guide
4.2.8 Modem Analog Interface This is a critical portion of the layout. Failure to do this correctly will result in poor modem performance. The signals between the transformer and the device are all analog signals. 1. 2. Conexant devices that connect to the transformer have an analog area separate from the digital. Keep them separate. Keep all digital signals away from the transformer and associated analog signals. Following is the list of critical analog signals that should never get near digital signals.
Signal TXA1 TXA2 RXA MIC_V VC
Routing Route in close proximity to TXA2. Route in close proximity to TXA1. Very sensitive; minimize trace length and its exposure to other signals, especially digital. Use a 12-mil trace. Very sensitive; minimize trace length and its exposure to other signals, especially digital. Very sensitive; place decoupling capacitor network as close as possible with the shortest path to AGND pin. Only then, tie to a good local analog ground. Use 12-mil or thicker traces. Use ferrite bead in AGND lead is necessary. Avoid loading by external circuits. Place decoupling capacitor network as close as possible. Use 12-mil or thicker traces.
VREF TELIN TELOUT
3. 4. 5.
Provide a separate local analog ground plane for the analog signals listed above. Rotate the modem device(s) so that the routing to the transformer is as short as possible. That way the traces can be short and the opportunity for digital signals to compromise the analog signals is decreased. Do not put vias on these signals.
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4.3 PCB LAYOUT EXAMPLES See Figure 4-1through Figure 4-4.
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RH56D-PCI Modem Designer's Guide
4.4 CRYSTAL/OSCILLATOR SPECIFICATIONS
Recommended surface-mount crystal specifications are listed in Table 4-1. Recommended through-hole crystal specifications are listed in Table 4-2.
4.5 OTHER CONSIDERATIONS
The DAA design described in this designer's guide is a wet DAA, i.e., it requires line current to be present to pass the signal. Therefore, if the modem is to be connected back-to-back by cable directly to another modem, the modems will not be able to connect. The DAAs must be modified to operate dry, i.e., without line current, when used in this environment.
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RH56D-PCI Modem Designer's Guide
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Characteristic Conexant Part No. Electrical Frequency Frequency Tolerance Frequency Stability vs. Temperature vs. Aging Oscillation Mode Calibration Mode Load Capacitance, CL Shunt Capacitance, CO Series Resistance, R1 Drive Level Operating Temperature Storage Temperature Mechanical Dimensions (L x W x H) Mounting Holder Type Suggested Suppliers KDS America ILSI America Vectron Technologies, Inc. Notes 1. Characteristics @ 25C unless otherwise noted. 2. Supplier Information: KDS America Fountain Valley, CA 92626 (714) 557-7833 ILSI America Kirkland, WA 98033 (206) 828 - 4886 Vectron Technologies, Inc. Lowell, NH 03051 (603) 598-0074 Toyocom U.S.A., Inc. Costa Mesa, CA (714) 668-9081 7.5 x 5.2 x 1.3 mm max. SMT None 5333R02-020
Value
28.224 MHz nom. 50 ppm (CL = 16.5 and 19.5 pF) 35 ppm (0C to 70C) 15 ppm/4 years Fundamental Parallel resonant 18 pF nom. 7 pF max. 60 max. @20 nW drive level 100W correlation; 300W max. 0C to 70C -40C to 85C
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RH56D-PCI Modem Designer's Guide
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Characteristic Conexant Part No. Electrical Frequency Frequency Tolerance Frequency Stability vs. Temperature vs. Aging Oscillation Mode Calibration Mode Load Capacitance, CL Shunt Capacitance, CO Series Resistance, R1 Drive Level Operating Temperature Storage Temperature Mechanical Dimensions (L x W x H) Mounting Holder Type Suggested Suppliers KDS America ILSI America Vectron Technologies, Inc. Notes 1. Characteristics @ 25C unless otherwise noted. 2. Supplier Information: KDS America Fountain Valley, CA 92626 (714) 557-7833 ILSI America Kirkland, WA 98033 (206) 828 - 4886 Vectron Technologies, Inc. Lowell, NH 03051 (603) 598-0074 Toyocom U.S.A., Inc. Costa Mesa, CA (714) 668-9081 11.05 x 4.65 x 13.46 mm max. Through Hole HC-49/U 333R44-011
Value
28.224 MHz nom. 50 ppm (CL = 16.5 and 19.5 pF) 30 ppm (0C to 70C) 20 ppm/5 years Fundamental Parallel resonant 18 pF nom. 7 pF max. 35 max. @20 nW drive level 100W correlation; 500W max. 0C to 70C -40C to 85C
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RH56D-PCI Modem Designer's Guide
4.6 PACKAGE DIMENSIONS
The package dimensions are shown in Figure 4-5 (144-pin TQFP).
D D1 D2
PIN 1 REF
D
D1 D2
D1
e
b DETAIL A
Dim. A
Millimeters Max. Min. 1.6 MAX 0.15 0.05 1.4 REF 22.25 21.75 20.0 REF 17.5 REF 0.75 0.5 1.0 REF 0.50 BSC 0.17 0.27 0.17 0.11 0.08 MAX
Inches* Max. Min. 0.0630 MAX 0.0020 0.0059 0.0551 REF 0.8563 0.8760 0.7874 REF 0.6890 REF 0.0197 0.0295 0.0394 REF 0.0197 BSC 0.0067 0.0043 0.0106 0.0067
D1
A1 A2 D D1 D2 L L1 e b c Coplanarity
A
A2
0.0031 MAX
Ref: 144-PIN TQFP (GP00-D252)
c A1 L1 DETAIL A
L
* Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors.
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RH56D-PCI Modem Designer's Guide 5. SOFTWARE INTERFACE
5.1 PCI CONFIGURATION REGISTERS
The PCI Configuration registers are located in the BIF. Table 5-1 identifies the configuration register contents that are supported in the BIF device:
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Bit Offset (Hex) 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 Max Latency Data Min Grant PMCSR_BSE Bridge Support Extensions Power Management Capabilities (PMC) Reserved Reserved Interrupt Pin Next Item Ptr Interrupt Line Capability ID Subsystem ID Not Implemented Cap Ptr Not Implemented 31:24 Device ID Status Class Code Header Type Latency Timer Base Address 0 - Memory (BIF) Base Address 1 - I/O (Dummy) Unused Base Address Register Unused Base Address Register Unused Base Address Register Unused Base Address Register CIS Pointer Subsystem Vendor ID 23:16 15:8 Vendor ID Command Revision ID Not Implemented 7:0
Power Management Control/Status Register (PMCSR)
5.1.1 0x00 - Vendor ID Field This field is read-only and is loaded from the serial EEPROM after reset events. The value is 14F1 for Conexant. 5.1.2 0x02 - Device ID Field This field is read-only and is loaded from the serial EEPROM after reset events.
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RH56D-PCI Modem Designer's Guide
5.1.3 0x04 - Command Register The Command Register bits are described in Table 5-2.
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Bit 0 1
Description Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses. The bit state is 0 after PCIRST# is deasserted. Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to Memory Space accesses. The bit state is 0 after PCIRST# is deasserted. Controls a device's ability to act as a master on the PCI Bus. A value of 0 disables the device from generating PCI accesses. A value of 1 allows the device to behave as a bus master. The bit state is 0 after PCIRST# is deasserted. Not Implemented. This bit controls the device's response to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is 0, the device must ignore any parity errors that it detects and continue normal operation. The bit state is 0 after PCIRST# is deasserted. This bit is used to control whether or not a device does address/data stepping. This bit is read only from the PCI interface. The bit state is loaded from the serial EEPROM after PCIRST# is deasserted. This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver. A value of 1 enables the SERR# driver. The bit state is 0 after PCIRST# is deasserted. This bit controls whether or not a master can do fast back-to-back transactions to different devices. A value of 1 means the master is allowed to generate fast back-to-back transactions to different agents as described in Section 3.4.2 of the PCI 2.1 specification. A value of 0 means fast back-to-back transactions are only allowed to the same agent. The bit state is 0 after PCIRST# is deasserted. Reserved
2
3-5 6
7 8 9
10-15
5.1.4 0x06 - Status Register The Status Register bits are described in Table 5-3. Status register bits may be cleared by writing a `1' in the bit position corresponding to the bit position to be cleared. It is not possible to set a status register bit by writing from the PCI Bus. Writing a `0' has no effect in any bit position.
7DEOH 6WDWXV 5HJLVWHU
Bit 0-3 4 5-7 8 Reserved
Description This bit is set to indicate the presence of the Capabilities Pointer pointing to Power Management registers (0x40, 0x44). Not Implemented. This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent asserted PERR# itself or observed PERR# asserted; 2) the agent setting the bit acted as the bus master for the operation in which the error occurred; and 3) the Parity Error Response bit (Command Register) is set. These bits encode the timing of DEVSEL#. These are encoded as 00 for fast, 01 for medium, and 10 for slow (11 is reserved.) These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command except Configuration Read and Configuration Write. Not Implemented. This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All master devices must implement this bit. This bit must be set by a master device whenever its transaction (except for Special Cycle) is terminated with Master-Abort. All master devices must implement this bit. This bit must be set whenever the device asserts SERR#. Devices which will never assert SERR# do not need to implement this bit. This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the Command register).
9-10
11 12 13 14 15
5-2
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RH56D-PCI Modem Designer's Guide
5.1.5 0x08 - Revision ID Field Value hardcoded in the device. 5.1.6 0x09 - Class Code Field Loaded from the serial EEPROM after after PCIRST# is deasserted. 5.1.7 0x0D - Latency Timer Register The Latency Timer register specifies, in units of PCI Bus clocks, the value of the Latency Timer for this PCI Bus master. This register has 5 read/write bits (MSBs) plus 3 bits of hardwired zero (LSBs). The Latency Timer Register is loaded into the PCI Latency counter each time FRAME# is asserted to determine how long the master is allowed to retain control of the PCI Bus. This register is loaded by system software. The default value for Latency Timer is 00. 5.1.8 0x0E - Header Type Field Hardwired to 00. 5.1.9 0x28 - CIS Pointer Register This register points to the CIS memory located in the BIF's memory space. 5.1.10 0x2C - Subsystem Vendor ID Register Subsystem Vendor ID register is supported. Loaded from the serial EEPROM after PCIRST# is deasserted. 5.1.11 0x2E- Subsystem ID Register Subsystem ID register is supported. Loaded from the serial EEPROM after PCIRST# is deasserted. 5.1.12 0x34 - Cap Ptr Capabilities Pointer (CAP_PTR) at offset 0x34 containing hardcoded value 0x40. 5.1.13 0x3C - Interrupt Line Register The Interrupt Line register is a read/write 8-bit register. POST software will write the value of this register as it initializes and configures the system. The value in this register indicates which of the system interrupt controllers the device's interrupt pin is connected to. 5.1.14 0x3D - Interrupt Pin Register The Interrupt Pin register tells which interrupt pin the device uses. The value of this register will be 0x01, indicating that INTA# will be used. 5.1.15 0x3E - Min Grant Register The Min Grant register is used to specify the devices desired settings for Latency Timer values. The value specifies a period of time in units of 0.25 microsecond. Min Grant is used for specifying the desired burst period assuming a 33 MHz clock. This register is loaded from the serial EEPROM after PCIRST# is deasserted. 5.1.16 0x3F - Max Latency Register The Max Latency register is used to specify the devices desired settings for Latency Timer values. The value specifies a period of time in units of 0.25 microsecond. Min Latency specifies how often the device needs to gain access to the PCI Bus. This register is loaded from the serial EEPROM after PCIRST# is deasserted. 5.1.17 0x40 - Capability Identifier The Capability Identifier is set to 01h to indicate that the data structure currently being pointed to is the PCI Power Management data structure. 5.1.18 0x41 - Next Item Pointer The Next Item Pointer register describes the location of the next item in the function's capability list. The value given is an offset into the function's PCI Configuration Space. The value of 00h indicates there are no additional items in the capabilities list.
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5-3
RH56D-PCI Modem Designer's Guide
5.1.19 0x42 - PMC - Power Management Capabilities The Power Management Capabilities register is a 16-bit read-only register which provides information on the capabilities of the function related to power management (Table 5-4).
7DEOH 3RZHU 0DQDJHPHQW &DSDELOLWLHV 30& 5HJLVWHU
Bit 2:0 3 4 5 8:6 9 10 15:11
R/W R R R R R R R R
Description Version. 010b indicates compliance with Revision 1.0 of the PCI Power Management Interface Specification. PME Clock. Hard coded to 0 to indicate that the PCI clock is not required for PME generation . Reserved (=0b). DSI (Device Specific Initialization). Loaded from serial EEPROM. Aux. Current. Loaded from serial EEPROM. D1_Support. When set to a 1, the BIF device supports D1 power state (loaded from serial EEPROM). D2_ Support. When set to a 1, the BIF device supports D2 power state (loaded from serial EEPROM). These 5 bits indicate which power states allow assertion of PME (loaded from serial EEPROM). A value of 0b for any bit indicates that the function cannot assert the PME# signal while in that power state. Bit 11: 1 = PME# can be asserted from D0 Bit 12: 1 = PME# can be asserted from D1 Bit 13: 1 = PME# can be asserted from D2 Bit 14 1 = PME# can be asserted from D3hot Bit 15 1 = PME# can be asserted from D3cold.
5.1.20 0x44 - PMCSR - Power Management Control/Status Register (Offset = 4) This 16-bit register is used to manage the PCI function's power management state as well as to enable/monitor power management events (Table 5-5).
7DEOH 3RZHU 0DQDJHPHQW &RQWURO6WDWXV 5HJLVWHU 30&65
Bit 1:0
R/W R/W Power State. 00 = D0 01 = D1 10 = D2 11 = D3. Reserved (= 000000b). PME_En. A 1 enables PME assertion.
Description
7:2 8 12:9 14:13 15:11
R R/W R/W R R/C
Data_Select. Selects Data and Data Scale fields. Data Scale. Associated with Data field. Loaded from serial EEPROM. PME_Status. This bit is sticky when PME assertion from D3_COLD is supported. PME_Status = 1 indicates PME asserted by the BIF device. Writing 1 clears PME_Status. Writing 0 has no effect.
R: Bit(s) is (are) read only. R/W: Bit(s) is (are) readable and writeable. R/C: Bit(s) is (are) readable, and clearable by writing 1 (bit may not be set by writing).
5.1.21 0x46 - PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions PMCSR_BSE is cleared to 0 to indicate that bus power/clock control policies have been disabled. 5.1.22 0x47 - Data This register is used to report the state dependent data requested by the Data_Select field. The value of this register is scaled by the value reported by the Data_Scale field.
5-4
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RH56D-PCI Modem Designer's Guide
5.2 BASE ADDRESS REGISTER
BIF provides a single Base Address Register. The Base Address Register is a 32 bit register that is used to access the BIF register set. Bits 3:0 are hard-wired to 0 to indicate memory space. Bits 15-4 will be hard-wired to 0. The remaining bits (31 16) will be read/write. This specifies that this device requires a 64k byte address space. After reset, the Base Address Register contains 0x00000000. The 64k byte address space used by the BIF is divided into 4k-byte regions. Each 4k-byte region is used as Table 5-6.
7DEOH %,) $GGUHVV 0DS
Address [15:12] 0x0 0x1 0x2 0x3 0x4 0x5-0xF
Address [11:0] 0x0-0xfff 0x0-0xfff 0x0-0xfff 0x0-0xfff 0x0-0xfff 0x0-0xfff
Region Name BASIC2 Registers CIS Memory DSP Scratch Pad Reserved Reserved Reserved.
Description Buffers, control, and status registers Data loaded from Serial EEPROM for Card Bus applications Access to DSP scratch pad registers
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5-5
RH56D-PCI Modem Designer's Guide
5.3 SERIAL EEPROM INTERFACE
The PCI Configuration Space Header and Power Management registers customizable fields are loaded from EEPROM during Power On Reset and during D3 to D0 power transition soft reset. If the EEPROM is missing, default hard-coded values are used. This section describes how the EEPROM content maps into the registers. The PCI Configuration Space Header and Power Management information is used by the PC BIOS/Windows OS to find the driver for this board and also to find out the extent PCI Power Management is typically supported on the modem board. 5.3.1 Supported EEPROM Sizes Two EEPROM sizes are supported: 256 by 16 bit (e.g., 93LC66B) as shown in Table 5-7 and 128 by 16 bit (e.g., 93LC56B) as shown in Table 5-8. The difference is the 256-word version supports modem default country selection from the EEPROM and also supports CardBus designs, whereas the 128-word version supports neither. The EEPROM text file used by the DOS4GW B2EPROM program utility lists the EEPROM content 8 bits per line in hexadecimal format. The least significant 8 bits are listed first followed by the most significant 8 bits of the 16-bit word.
7DEOH ((3520 &RQWHQW IRU :RUGV E\ %LWV SHU :RUG
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F-FE FF
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device ID Vendor ID Subsystem Device ID Subsystem Vendor ID Don't Care Max_Lat PMC bit 8 Sub-Class Code PMC bit 7 PMC bit 6 PME DRV Min_Gnt Class Code Prog. I/F CardBus CIS Pointer High CardBus CIS Pointer Low D3C D0D
D0C
D3_ Cold
D3_ Hot
D1C D2C D3 power consumed D1 power consumed D3 power dissipated D1 power dissipated D2 D1 D0 D2_ State Don't Care Don't Care
D1_ State
DSI
D1D D2D D2 power consumed D0 power consumed D2 power dissipated D0 power dissipated Load CISRAM Count Don't Care Don't Care
D3D
7DEOH ((3520 &RQWHQW IRU :RUGV E\ %LWV SHU :RUG
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F-7F
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device ID Vendor ID Subsystem Device ID Subsystem Vendor ID Don't Care Max_Lat PMC bit 8 Sub-Class Code PMC bit 7 PMC bit 6 PME DRV Min_Gnt Class Code Prog. I/F CardBus CIS Pointer High CardBus CIS Pointer Low D3C D0D
D0C
D3_ Cold
D3_ Hot
D1C D2C D3 power consumed D1 power consumed D3 power dissipated D1 power dissipated D2 D1 D0 D2_ State Don't Care
D1_ State
DSI
D1D D2D D2 power consumed D0 power consumed D2 power dissipated D0 power dissipated Load CISRAM Count Don't Care
D3D
5-6
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RH56D-PCI Modem Designer's Guide
5.3.2 Definitions Device ID Register This mandatory 16-bit register identifies the type of device and is assigned by Conexant. Valid values are: RH56D-PCI Data/Fax has a Device ID of 1033. RH56D-PCI Data/Fax/Remote TAM has a Device ID of 1034. RH56D-PCI/SP Data/Fax/Voice/Speakerphone has a Device ID of 1035. Vendor ID Register This mandatory 16-bit register identifies the manufacturer of the device. The value in this read-only register is assigned by a central authority (i.e., the PCI SIG) that controls the issuance of the numbers. The value is 14F1 for Conexant. Subsystem Vendor ID and Subsystem Device Register The subsystem vendor ID is obtained from the SIG, while the vendor supplies its own subsystem device ID. These values are supplied by OEM. Until these values are assigned, Conexant uses default values for Subsystem Vendor ID and Subsystem Device ID which are the same as Vendor ID and Device ID, respectively. A PCI functional device may be contained on a card or be embedded within a subsystem. Two cards or subsystems that use the same PCI functional device core logic would have the same vendor and device IDs. These two optional registers are used to uniquely identify the add-in card or subsystem that the functional device resides within. Software can then distinguish the difference between cards or subsystems manufactured by different vendors but with the same PCI functional device on the card or subsystem. A value of zero in these registers indicates that there isn't a subsystem vendor and subsystem ID associated with the device. Min_Gnt Register This register is assigned by Conexant. The value is 00. This register is optional for a bus master and not applicable to non-master devices. This register indicates how long the master would like to retain PCI Bus ownership whenever it initiates a transaction. The value hardwired into this register indicates how long a burst period the device needs (in increments of 250 ns). A value of zero indicates the device has no stringent requirements in this area. This information is useful in programming the algorithm to be used in the PCI Bus arbiter (if it is programmable). Max_Lat Register This register is assigned by Conexant. The value is 00. This register is optional for a bus master and not applicable to non-master devices. The specification states that this read-only register specifies "how often" the device needs access to the PCI Bus (in increments of 250 ns). A value of zero indicates the device has no stringent requirements for the data. This register could be used to determine the priority-level the bus arbiter assigns to the master.
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5-7
RH56D-PCI Modem Designer's Guide
PMC [8:6], PME DRV Type This register is assigned by Conexant. The value is 01. PMC [8:6]: This 3- bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If the Data Register has been implemented by this function then 1) reads of this field must return a value of "000b" 2) Data Register takes precedence over this field for 3.3Vaux current requirements. If PME# generation from D3cold is not supported by the function (PMC(15)=0), then this field must return a value of "000b" when read. PME DRV Type: This sets the driving capability of the PME pin (0 = active high TTL, 1 = active low Open Drain) Class Code Register (Class Code, Sub-class Code, Prog. I/F) This register is always mandatory and is assigned by Conexant. The value is 07 for Class Code, 80 for Sub-class code, and 00 for Prog. I/F. This register is a 24-bit read-only register divided into three sub-registers: base class, sub-class, and Prog. I/F (programming interface). The register identifies the basic function of the device via the base class (i.e. for modems: Simple Communications Controller), a more specific device sub-class (i.e. for modems: Other Communications Device), and in some cases a registerspecific programming interface (not used for modems). CardBus CIS Pointer (CardBus CIS pointer High, CardBus CIS pointer Low) This register is optional and is assigned by Conexant. The value is 00000000. This optional register is implemented by devices that share silicon between CardBus and PCI. This field points to the card information structure, or CIS, for the CardBus card. This register is read-only and contains the offset of the CIS. Data Scale PMCSR[14:13] (D0C, D1C, D2C, D3C, D0D, D1D, D2D, D3D) This value is supplied by the OEM since Conexant implements the Data Register. Until these values are assigned, Conexant uses a default value 0000. This field is required for any function that implements the Data Register. The data scale is a 2- bit read-only field which indicates the scaling factor to be used when interpreting the value of the Data Register. The value and meaning of this field will vary depending on which data value has been selected by the Data_Select field (PMCSR[12:09]). There are 4 data scales to select 1) 0 = unknown 2) 1 = 0.1x, 3) 2 = 0.01x, 4) 3 = 0.001x where x is defined by the Data Select Field. Data Register (D3, D2, D1, D0 power consumed and D3, D2, D1, D0 power dissipated) This value is supplied by the OEM since Conexant implements the Data Register. Until these values are assigned, Conexant uses a default value of 0000000000000000. The Data Register is an optional, 8-bit read-only register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. Typically the data returned through the Data register is a static copy (look up table, for example) of the function's worst case "DC characteristics" data sheet. This data, when made available to system software could then be used to intelligently make decisions about power budgeting, cooling requirements, etc. The data returned by the data register is selected by the Data Select field (PMCSR[12:09]). Load CISRAM Count (CIS _SIZE) This register is optional and is assigned by Conexant. The value is 00. This register contains an 8-bit value indicating the number of double words to be loaded into the CISRAM for CardBus support. PMC[15:9, 5] (D3_Cold, D3_Hot, D2, D1, D0, D2_Support, D1_Support, DSI) PMC[15:11]: PME_Support (D3_Cold, D3_Hot, D2, D1, D0)- This five bit field indicates the power states in which the function may assert PME#. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. D2 and D1 must be 0 since the modem does not support these states. The rest of the values are supplied by the OEM and the values depend upon the systems in which the modem will be installed. Conexant uses a default value of 49. This is for a system which does not support D3cold but supports D3hot. When D3_Cold is a 1, PMC[15] is set to a 1 if VauxDET is high at device power on reset (POR) or is reset to a 0 if VauxDET is low at POR. When D3_Cold is a 0, PMC[15] is always 0, regardless of the VauxDET level.
5-8
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RH56D-PCI Modem Designer's Guide
PMC[10] (D2_Support): If this bit is a 1 then function supports the D2 Power Management State. Currently the modems do not support this state and therefore this field must be 0. PMC[9] (D1_Support): If this bit is a 1 then function supports the D1 Power Management State. Currently the modems do not support this state and therefore this field must be 0. DSI: The Device Specific Initialization bit indicates whether special initialization of this function is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. This bit should always be set to "1".
NOTE: For more information, refer to PCI Bus Power Management Interface Specification.
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RH56D-PCI Modem Designer's Guide
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5-10
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NOTES (Inside Back Cover)
Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com
Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440
World Headquarters
Conexant Systems, Inc. 4311 Jamboree Road P. O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (813) 799-8406 Fax: (813) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (770) 246-8283 Fax: (770) 246-0018 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090
Europe Headquarters
Conexant Systems France Les Taissounieres B1 1680 Route des Dolines BP 283 06905 Sophia Antipolis Cedex France Phone: (33 4) 93 00 33 35 Fax: (33 4) 93 00 33 03 Europe Central Phone: (49 89) 829 1320 Fax: (49 89) 834 2734 Europe Mediterranean Phone: (39 02) 9317 9911 Fax: (39 02) 9317 9913 Europe North Phone: (44 1344) 486 444 Fax: (44 1344) 486 555 Europe South Phone: (33 1) 41 44 36 50 Fax: (33 1) 41 44 36 90
Middle East Headquarters
Conexant Systems Commercial (Israel) Ltd. P. O. Box 12660 Herzlia 46733, Israel Phone: (972 9) 952 4064 Fax: (972 9) 951 3924
Japan Headquarters
Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 Japan Phone: (81 3) 5371-1567 Fax: (81 3) 5371-1501
APAC Headquarters
Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower Singapore 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd. Room 2808, 333 International Trade Building Keelung Road, Section 1 Taipei 110, Taiwan, ROC Phone: (886 2) 2720 0282 Fax: (886 2) 2757 6760
SO990121

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